Huy Nam Nguyen

14 papers C 6Unranked 8
YearRankTypeTitle / Venue / Authors
2007 C conf
An QoS Aware Mapping of Cores Onto NoC Architectures.
ISPA
Huy Nam Nguyen, Vu-Duc Ngo, Younghwan Bae, Hanjin Cho, Hae-Wook Choi
2006 C conf
The Optimum Network on Chip Architectures for Video Object Plane Decoder Design.
ISPA
Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
2006 — conf
Throughput Aware Mapping for Network on Chip Design of H.264 Decoder.
ISPA Workshops
Vu-Duc Ngo, Huy Nam Nguyen, Younghwan Bae, Hanjin Cho, Hae-Wook Choi
2005 C conf
Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design.
EUC
Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
2005 — conf
Designing On-Chip Network Based on Optimal Latency Criteria.
ICESS
Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
2005 — conf
Realization of Video Object Plane Decoder on On-Chip Network Architecture.
ICESS
Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi
2005 — conf
Realization of video object plane decoder on mesh on-chip network architecture.
Circuits, Signals, and Systems
Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi
1996 C conf
Design Verification based on Hardware Emulation.
RSP
Huy Nam Nguyen, Michel Thill
1995 C conf
Application of synthesis to support hardware emulation.
RSP
Huy Nam Nguyen, Yvon Gressus, Michel D'Hoe
1995 — conf
Auriga2: a 4.7 million-transistor CISC microprocessor.
ASP-DAC
J. P. Tual, Michel Thill, C. Bernard, Huy Nam Nguyen, F. Mottini, M. Moreau, P. Vallet
1994 — conf
Logic Synthesis and Verification of the CPU and Caches of a Mainframe System.
EDAC-ETC-EUROASIC
Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet
1994 C conf
The Structured Logic CAD Suite Used on the DPS7000 System.
ICCD
Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet
1989 — conf
Automated synthesis of combinational logic using problem solving techniques.
SPLT
Huy Nam Nguyen, L. Ducousso
1988 — conf
Utilisation de CHIP pour la synthèse et vérification des circuits CMOS.
SPLT
Huy Nam Nguyen, L. Ducousso