Huseyin Ekin Sumbul

23 papers A* 1A 2Journal 6Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint. DATE Huseyin Ekin Sumbul, Arne Symons, Lita Yang, Huichu Liu, Tony F. Wu, Matheus Trevisan Moreira, Debabrata Mohapatra, Abhinav Agarwal, Kaushik Ravindran, Chris Thompson, Yuecheng Li, Edith Beigné
2025	J	`jnl`	Re-CATA: Real-Time and Flexible Accelerator Design Framework for On-Device Codec Avatars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yongan Zhang, Yuecheng Li, Syed Shakib Sarwar, Huseyin Ekin Sumbul, Yonggan Fu, Haoran You, Cheng Wan, Yingyan Lin
2024	—	`conf`	11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. ISSCC Tony F. Wu, Huichu Liu, Huseyin Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné
2024	J	`jnl`	A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. IEEE Micro Huseyin Ekin Sumbul, Jae-sun Seo, Daniel H. Morris, Edith Beigné
2024	—	`conf`	Characterization and Design of 3D-Stacked Memory for Image Signal Processing on AR/VR Devices. MEMSYS Lita Yang, Changjung Kao, Sriseshan Srikanth, Huseyin Ekin Sumbul, Tony F. Wu, Huichu Liu, Edith Beigné
2023	—	`conf`	A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. ASYNC Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné
2022	A	`conf`	A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows. DATE Linyan Mei, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Marian Verhelst, Edith Beigné
2022	—	`conf`	Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications. VLSI Technology and Circuits Daniel H. Morris, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Elnaz Ansari, Alexandre Barachant, Jonathan Reid, Edith Beigné
2022	J	`jnl`	DRESS: Dynamic REal-time Sparse Subnets. CoRR Zhongnan Qu, Syed Shakib Sarwar, Xin Dong, Yuecheng Li, Huseyin Ekin Sumbul, Barbara De Salvo
2022	J	`jnl`	Power-of-Two Quantization for Low Bitwidth and Hardware Compliant Neural Networks. CoRR Dominika Przewlocka-Rus, Syed Shakib Sarwar, Huseyin Ekin Sumbul, Yuecheng Li, Barbara De Salvo
2022	—	`conf`	System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars. CICC Huseyin Ekin Sumbul, Tony F. Wu, Yuecheng Li, Syed Shakib Sarwar, William Koven, Eli Murphy-Trotzky, Xingxing Cai, Elnaz Ansari, Daniel H. Morris, Huichu Liu, Doyun Kim, Edith Beigné
2021	J	`jnl`	A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. IEEE J. Solid State Circuits Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy
2020	—	`conf`	25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De
2020	—	`conf`	A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. VLSI Circuits Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy
2019	J	`jnl`	A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS. IEEE J. Solid State Circuits Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy
2018	—	`conf`	A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS. VLSI Circuits Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy
2015	—	`—`	A Novel Design Methodology for Synthesizing Application-Specific Logic-in-Memory Blocks. Huseyin Ekin Sumbul
2015	A*	`conf`	A synthesis methodology for application-specific logic-in-memory designs. DAC Huseyin Ekin Sumbul, Kaushik Vaidyanathan, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi
2014	—	`conf`	Building trusted ICs using split fabrication. HOST Kaushik Vaidyanathan, Bishnu Prasad Das, Huseyin Ekin Sumbul, Renzhi Liu, Larry T. Pileggi
2014	—	`conf`	Efficient and secure intellectual property (IP) design with split fabrication. HOST Kaushik Vaidyanathan, Renzhi Liu, Huseyin Ekin Sumbul, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi
2013	—	`conf`	A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. 3DIC Qiuling Zhu, Berkin Akin, Huseyin Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry T. Pileggi, Franz Franchetti
2013	—	`conf`	Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware. HPEC Qiuling Zhu, Tobias Graf, Huseyin Ekin Sumbul, Larry T. Pileggi, Franz Franchetti
2010	—	`conf`	Fast Smith-Waterman hardware implementation. IPDPS Workshops Zubair Nawaz, Koen Bertels, Huseyin Ekin Sumbul