Hung Tien Bui

15 papers C 5Journal 1Unranked 9
YearRankTypeTitle / Venue / Authors
2013 — conf
Design of low power 4-bit flash ADC based on standard cells.
NEWCAS
Marcel Siadjine Njinowa, Hung Tien Bui, François-Raymond Boyer
2012 C conf
Pipelined FPGA design of the Goertzel algorithm for exon prediction.
ISCAS
Hung Tien Bui
2011 C conf
Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon prediction.
ISCAS
Michel Voyer, Sylvain-Robert Rivard, Luc Morin, Hung Tien Bui
2010 C conf
Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS).
ISCAS
Marcel Siadjine Njinowa, Hung Tien Bui, François R. Boyer
2010 — conf
Sensorless vector control of PMSG for variable speed wind energy applications.
CCECE
Jogendra Singh Thongam, Pierre Bouchard, Valentin Giurgiu, Hung Tien Bui, Mohand A. Ouhrouche
2008 J jnl
Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hung Tien Bui, Yvon Savaria
2008 C conf
Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis.
ISCAS
Hung Tien Bui
2008 — conf
High speed CDR using a novel binary phase detector with probable-lock-detection.
ICECS
Hung Tien Bui
2007 C conf
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.
ISCAS
Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria
2006 — conf
Dual-Path and Diode-Tracking Active Inductors for MCML Gates.
CCECE
Hung Tien Bui
2006 — conf
High speed differential pulse-width control loop based on frequency-to-voltage converters.
ACM Great Lakes Symposium on VLSI
Hung Tien Bui, Yvon Savaria
2005 — conf
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs.
IWSOC
Hung Tien Bui, Yvon Savaria
2004 — conf
10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.
IWSOC
Hung Tien Bui, Yvon Savaria
2004 — conf
Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector.
ISCAS (4)
Hung Tien Bui, Yvon Savaria
2001 — conf
Five new high-performance multiplexer-based 1-bit full adder cells.
ICECS
Abdulkarim Al-Sheraidah, Bassem Alhalabi, Hung Tien Bui