Hung C. Ngo

11 papers A 1C 2Misc 1Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2009 J jnl
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits
Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer
2008 J jnl
Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.
IEEE Trans. Very Large Scale Integr. Syst.
Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, Fadi H. Gebara, Kevin J. Nowka
2008 A conf
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
ISLPED
Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif
2006 Misc conf
Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems.
VLSI Design
Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown
2006 J jnl
Limited switch dynamic logic circuits for high-speed low-power circuit design.
IBM J. Res. Dev.
Wendy Belluomini, Damir Jamsek, Andrew K. Martin, Chandler McDowell, Robert K. Montoye, Hung C. Ngo, Jun Sawada
2005 C conf
A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.
ICCD
Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi
2005 — conf
Controlled-Load Limited Switch Dynamic Logic Circuit.
ISQED
Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown
2004 — conf
A low latency and low power dynamic Carry Save Adder.
ISCAS (2)
Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka
2002 J jnl
A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling.
IEEE J. Solid State Circuits
Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns
1998 J jnl
A 1.0-GHz single-issue 64-bit powerPC integer processor.
IEEE J. Solid State Circuits
Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric
1998 C conf
Design methodology for a 1.0 GHz microprocessor.
ICCD
Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo