Hui Wang

43 papers A 1C 3Misc 1Journal 18Unranked 20
YearRankTypeTitle / Venue / Authors
2019 J jnl
Designing scrubbing strategy for memories suffering MCUs through the selection of optimal interleaving distance.
Int. J. Comput. Sci. Eng.
Wei Zhou, Hong Zhang, Hui Wang, Yun Wang
2016 C conf
Energy-efficient task scheduling for DVFS-enabled heterogeneous computing systems using a linear programming approach.
IPCCC
Yujian Zhang, Yun Wang, Hui Wang
2016 — conf
ISS: An Iterative Scrubbing Strategy for Improving Memory Reliability Against MBU.
HCC
Hui Wang, Yun Wang
2015 J jnl
Superset: a non-uniform replica placement strategy towards perfect load balance and fine-grained power proportionality.
Clust. Comput.
Xiangyu Luo, Gang Xin, Yun Wang, Zexi Zhang, Hui Wang
2014 J jnl
A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xueqing Li, Qi Wei, Zhen Xu, Jianan Liu, Hui Wang, Huazhong Yang
2014 — conf
A single channel, 6-bit 410-ms/s asynchronous SAR ADC based on 3bits/stage.
NEWCAS
Xue Han, Nan Zhao, Qi Wei, Fei Qiao, Huazhong Yang, Hui Wang
2013 J jnl
Design Methodology of the Heterogeneous Multi-core Processor With the Combination of Parallelized Multi-core Simulator and Common Register File-Based Instruction Set Extension Architecture.
J. Comput.
Bingbing Xia, Fei Qiao, Huazhong Yang, Hui Wang
2013 — conf
HS3DPG: Hierarchical simulation for 3D P/G network.
ASP-DAC
Shuai Tao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang
2013 — conf
Superset: A Non-uniform Replica Placement Strategy towards High-Performance and Cost-Effective Distributed Storage Service.
CBD
Xiangyu Luo, Yun Wang, Zexi Zhang, Hui Wang
2013 — conf
Understanding Iterative Redundancy for Vulnerability-Driven Fault Tolerance Strategy.
ICPCA/SWS
Hui Wang, Yun Wang, Ling Zhou, Kun Jiang
2012 C conf
A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme.
ISCAS
Bo Zhao, Huazhong Yang, Hui Wang
2011 J jnl
A Low-Power IF Circuit with 5 dB Minimum Input SNR for GFSK Low-IF Receivers.
IEICE Trans. Electron.
Bo Zhao, Guangming Yu, Tao Chen, Pengpeng Chen, Huazhong Yang, Hui Wang
2011 C conf
Low-Power Off-Chip Memory Design for Video Decoder Using Embedded Bus-Invert Coding.
ISADS
Ni Zhou, Fei Qiao, Huazhong Yang, Hui Wang
2010 — conf
A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design.
ISQED
Bingbing Xia, Fei Qiao, Huazhong Yang, Hui Wang
2010 J jnl
Evaluation of Tunable Data Compression in Energy-Aware Wireless Sensor Networks.
Sensors
Beihua Ying, Yongpan Liu, Huazhong Yang, Hui Wang
2010 J jnl
Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting.
IET Circuits Devices Syst.
Guangming Yu, Yu Wang, Huazhong Yang, Hui Wang
2010 J jnl
Lightweight Precision-Adaptive Time Synchronization in Wireless Sensor Networks.
IEICE Trans. Commun.
Li Li, Yongpan Liu, Huazhong Yang, Hui Wang
2010 J jnl
Output remapping technique for critical paths soft-error rate reduction.
IET Comput. Digit. Tech.
Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang
2009 J jnl
A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design
CoRR
Bingbing Xia, Fei Qiao, Huazhong Yang, Hui Wang
2009 — conf
Energy efficient architecture of sensor network node based on compression accelerator.
ACM Great Lakes Symposium on VLSI
Jue Wang, Beihua Ying, Yongpan Liu, Huazhong Yang, Hui Wang
2008 J jnl
Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection.
Sci. China Ser. F Inf. Sci.
Fei Qiao, Huazhong Yang, Gang Huang, Hui Wang
2008 — conf
Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths.
ISQED
Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang
2008 J jnl
Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Yu Wang, Ku He, Rong Luo, Hui Wang, Huazhong Yang
2007 — conf
A Hybrid Genetic Algorithm with Critical Primary Inputs Sharing and Minor Primary Inputs Bits Climbing for Circuit Maximum Power Estimation.
ICNC (4)
Zhixin Tian, Yongpan Liu, Huazhong Yang, Hui Wang
2007 J jnl
Modified Conditional-Precharge Sense-amplifier-Based Flip-Flop with Improved Speed.
J. Circuits Syst. Comput.
Fei Qiao, Huazhong Yang, Dingli Wei, Hui Wang
2007 J jnl
Phase noise analysis of oscillators with Sylvester representation for periodic time-varying modulus matrix by regular perturbations.
Sci. China Ser. F Inf. Sci.
JianXing Fan, Huazhong Yang, Hui Wang, Xiaolang Yan, Chaohuan Hou
2007 — conf
Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems.
ISQED
Yongpan Liu, Huazhong Yang, Robert P. Dick, Hui Wang, Li Shang
2006 — conf
A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET Devices.
APCCAS
Saihua Lin, Rong Luo, Huazhong Yang, Hui Wang
2006 Misc conf
A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator.
VLSI Design
Jun Chen, Rong Luo, Huazhong Yang, Hui Wang
2006 — conf
A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection.
APCCAS
Yongpan Liu, Yu Wang, Feng Zhang, Rong Luo, Hui Wang
2006 — conf
Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate.
APCCAS
Yu Wang, Hui Wang, Huazhong Yang
2006 — conf
IR-drop Reduction Through Combinational Circuit Partitioning.
PATMOS
Hai Lin, Yu Wang, Rong Luo, Huazhong Yang, Hui Wang
2006 — conf
Modeling the Impact of Process Variation on Critical Charge Distribution.
SoCC
Qian Ding, Rong Luo, Hui Wang, Huazhong Yang, Yuan Xie
2006 — conf
Sigma-delta based clock recovery using on-chip PLL in FPGA.
FPT
Ning Ge, Yuyu Liu, Huazhong Yang, Hui Wang
2006 J jnl
Signal-Path-Level Dual-V
J. Circuits Syst. Comput.
Yu Wang, Huazhong Yang, Hui Wang
2006 — conf
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization.
ISQED
Yu Wang, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang
2006 A conf
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.
ISLPED
Yu Wang, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang
2005 — conf
A Hierarchical Approach for Incremental Floorplan Based on Genetic Algorithms.
ICNC (3)
Yongpan Liu, Huazhong Yang, Rong Luo, Hui Wang
2005 J jnl
Application of DAPSK in HF communications.
IEEE Commun. Lett.
Shuzheng Xu, Huazhong Yang, Hui Wang
2005 — conf
Improved Multiuser Detection for Fast FH/MFSK Systems.
ICWN
Hui Zhang, Huazhong Yang, Shuzheng Xu, Hui Wang
2002 J jnl
An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits.
Sci. China Ser. F Inf. Sci.
Gang Huang, Huazhong Yang, Rong Luo, Hui Wang
2001 J jnl
Noise estimation for deep sub-micron integrated circuits.
Sci. China Ser. F Inf. Sci.
Bin Chen, Huazhong Yang, Hui Wang
1999 — conf
An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits.
ASP-DAC
Huazhong Yang, Rong Luo, Hui Wang, Runsheng Liu