Hugh McIntyre

11 papers Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
Navigating the blue frontier: A review of machine learning approaches for sustainable marine bioresource utilization.
Ecol. Informatics
Oraléou Sangué Djandja, Xiaomei Zhong, Jie Yang, Hugh McIntyre, Quan Sophia He, Usman Ali
2025 J jnl
Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator.
IEEE Micro
Alan Smith, Gabriel H. Loh, Samuel Naffziger, John J. Wuu, Nathan Kalyanasundharam, Eric Chapman, Raja Swaminathan, Tyrone Huang, Wonjun Jung, Alexander Kaganov, Hugh McIntyre, Ramon Mangaser
2024 — conf
11.1 AMD InstinctTM MI300 Series Modular Chiplet Package - HPC and AI Accelerator for Exa-Class Systems.
ISSCC
Alan Smith, Eric Chapman, Chintan Patel, Raja Swaminathan, John J. Wuu, Tyrone Huang, Wonjun Jung, Alexander Kaganov, Hugh McIntyre, Ramon Mangaser
2024 — conf
AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization.
VLSI Technology and Circuits
Alan Smith, Gabriel H. Loh, John J. Wuu, Samuel Naffziger, Tyrone Huang, Hugh McIntyre, Ramon Mangaser, Wonjun Jung, Raja Swaminathan
2017 — conf
3.2 Zen: A next-generation high-performance ×86 core.
ISSCC
Teja Singh, Sundar Rangarajan, Deepesh John, Carson Henrion, Shane Southard, Hugh McIntyre, Amy Novak, Stephen Kosonocky, Ravi Jotwani, Alex Schaefer, Edward Chang, Joshua Bell, Michael Co
2016 J jnl
Carrizo: A High Performance, Energy Efficient 28 nm APU.
IEEE J. Solid State Circuits
Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox
2015 — conf
4.8 A 28nm x86 APU optimized for power and area efficiency.
ISSCC
Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White
2012 J jnl
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS.
IEEE J. Solid State Circuits
Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh
2011 — conf
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU.
ISSCC
Tim C. Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox
2005 J jnl
A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor.
IEEE J. Solid State Circuits
Hugh McIntyre, Dennis Wendell, K. James Lin, P. Kaushik, Suresh Seshadri, Alfred Wang, V. Sundararaman, Ping Wang, Song Kim, Wen-Jay Hsu, Hee-Choul Park, Gideon Levinsky, Jiejun Lu, M. Chirania, Raymond A. Heald, Paul Lazar, Sanjaya Dharmasena
2000 J jnl
A third-generation SPARC V9 64-b microprocessor.
IEEE J. Solid State Circuits
Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You