Hubert Kaeslin

53 papers A* 2A 5B 1C 8Journal 17Unranked 19
YearRankTypeTitle / Venue / Authors
2018 J jnl
Towards Edge-Aware Spatio-Temporal Filtering in Real-Time.
IEEE Trans. Image Process.
Michael Schaffner, Florian Scheidegger, Lukas Cavigelli, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2016 J jnl
Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW.
IEEE Trans. Circuits Syst. Video Technol.
Michael Schaffner, Frank K. Gürkaynak, Pierre Greisen, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2015 C conf
Automatic multiview synthesis - Prototype demo.
VCIP
Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2015 C conf
Automatic multiview synthesis - Towards a mobile system on a chip.
VCIP
Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2015 — ch.
Semiconductor Technology and the Energy Efficiency of ICT.
ICT Innovations for Sustainability
Hubert Kaeslin
2014 A* conf
An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing.
DAC
Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini
2014 C conf
Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers.
ISCAS
Christoph Keller, Frank K. Gürkaynak, Hubert Kaeslin, Norbert Felber
2014 — conf
SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC.
ASAP
Michael Gautschi, Michael Muehlberghuber, Andreas Traber, Sven Stucki, Matthias Baer, Renzo Andri, Luca Benini, Beat Muheim, Hubert Kaeslin
2013 — conf
A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized.
VLSI-SoC (Selected Papers)
Michael Schaffner, Pascal A. Hager, Lukas Cavigelli, Z. Fang, Pierre Greisen, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini
2013 C conf
A real-time 720p feature extraction core based on Semantic Kernels Binarized.
VLSI-SoC
Michael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin
2013 J jnl
Evaluation and FPGA Implementation of Sparse Linear Solvers for Video Processing Applications.
IEEE Trans. Circuits Syst. Video Technol.
Pierre Greisen, Marian Runo, Patrice Guillet, Simon Heinzle, Aljoscha Smolic, Hubert Kaeslin, Markus H. Gross
2013 C conf
Live demonstration: Real-time audio restoration using sparse signal recovery.
ISCAS
David E. Bellasi, Patrick Maechler, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer
2013 — conf
MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping.
ESSCIRC
Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gürkaynak, Hubert Kaeslin, Aljoscha Smolic
2012 J jnl
Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications.
IEEE Trans. Circuits Syst. Video Technol.
Pierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus H. Gross
2012 — conf
Compressive sensing for WiFi-based passive bistatic radar.
EUSIPCO
Patrick Maechler, Norbert Felber, Hubert Kaeslin
2012 C conf
Hardware-efficient random sampling of fourier-sparse signals.
ISCAS
Patrick Maechler, Norbert Felber, Hubert Kaeslin, Andreas Burg
2012 — conf
High-speed compressed sensing reconstruction on FPGA using OMP and AMP.
ICECS
Lin Bai, Patrick Maechler, Michael Muehlberghuber, Hubert Kaeslin
2012 — conf
Sparsity-based real-time audio restoration.
DASIP
Patrick Maechler, David E. Bellasi, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer
2012 J jnl
VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Patrick Maechler, Christoph Studer, David E. Bellasi, Arian Maleki, Andreas Burg, Norbert Felber, Hubert Kaeslin, Richard G. Baraniuk
2008 — conf
Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison.
APCCAS
Peter Luethi, Christoph Studer, Sebastian Duetsch, Eugen Zgraggen, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2008 J jnl
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.
IEEE Trans. Very Large Scale Integr. Syst.
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
2007 — conf
A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication.
CICC
Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
2007 J jnl
A hardware architecture for surface splatting.
ACM Trans. Graph.
Tim Weyrich, Simon Heinzle, Timo Aila, Daniel Bernhard Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, Markus H. Gross
2006 C conf
42% power savings through glitch-reducing clocking strategy in a hearing aid application.
ISCAS
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
2006 — conf
GALS at ETH Zurich: Success or Failure.
ASYNC
Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2006 A* conf
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm.
DAC
Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2006 A conf
Two-phase resonant clocking for ultra-low-power hearing aid applications.
DATE
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
2005 — conf
A 0.67-mm
ECCTD
Flavio Carbognani, Felix Bürgin, Luca Henzen, Herbert Koch, Hovig Magdassian, Christoph Pedretti, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2005 — conf
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC.
FMGALS@MEMOCODE
Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2005 — conf
Improving DPA security by using globally-asynchronous locally-synchronous systems.
ESSCIRC
Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2005 — conf
Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.
PATMOS
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
2004 — conf
A 2 Gb/s balanced AES crypto-chip implementation.
ACM Great Lakes Symposium on VLSI
Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin
2004 — conf
Towards an AES crypto-chip resistant to differential power analysis.
ESSCIRC
Norbert Pramstaller, Frank K. Gürkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2003 — conf
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems.
ASYNC
Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner
2003 — conf
Variable delay ripple carry adder with carry chain interrupt detection.
ISCAS (5)
Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner
2003 J jnl
Waveform coding for low-power digital filtering of speech data.
IEEE Trans. Signal Process.
Jürgen Wassner, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2002 A conf
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis.
CHES
Adrian K. Lutz, Jürg Treichler, Frank K. Gürkaynak, Hubert Kaeslin, Gérard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner
2002 — conf
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems.
ASYNC
Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
2001 J jnl
Design and Verification of a Stack Processor Virtual Component.
IEEE Micro
Manfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
2000 — conf
A new paradigm for very flexible SONET/SDH IP-modules.
CICC
Thomas Roewer, Manfred Stadler, Markus Thalmann, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
1999 A conf
Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor.
ITC
Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann
1997 J jnl
The impact of transistor sizing on power efficiency in submicron CMOS circuits.
IEEE J. Solid State Circuits
Robert Rogenmoser, Hubert Kaeslin
1996 A conf
Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits.
PPSN
Robert Rogenmoser, Hubert Kaeslin, Tobias Blickle
1994 J jnl
A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm.
IEEE J. Solid State Circuits
Reto Zimmermann, Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
1993 A conf
VINCI: Secure Test of a VLSI High-Speed Encryption System.
ITC
Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Reto Zimmermann, Wolfgang Fichtner
1991 J jnl
Regular VLSI architectures for multiplication modulo (2
IEEE J. Solid State Circuits
Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin
1991 C conf
VLSI Implementation of a New Block Cipher.
ICCD
Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai
1989 J jnl
Architectural design and realization of a single-chip Viterbi decoder.
Integr.
Marc Biver, Hubert Kaeslin, Carlo Tommasini
1989 J jnl
In-place updating of path metrics in Viterbi decoders.
IEEE J. Solid State Circuits
Marc Biver, Hubert Kaeslin, Carlo Tommasini
1988 B conf
Application of Graph Theory to Topology Generation for Logic Gates.
WG
Hubert Kaeslin
1988 J jnl
Behandlung der Umlaute bei der Verarbeitung deutscher Texte unter UNIX / How to Handle German Umlauts when Processing Documents under UNIX.
it Inf. Technol.
Hubert Kaeslin
1986 J jnl
A comparative study of the steady-state zones of German phones using centroids in the LPC parameter space.
Speech Commun.
Hubert Kaeslin
1986 J jnl
A systematic approach to the extraction of diphone elements from natural speech.
IEEE Trans. Acoust. Speech Signal Process.
Hubert Kaeslin