Hubert Harrer

14 papers C 1Journal 10Unranked 2
YearRankTypeTitle / Venue / Authors
2022 — conf
IBM Telum: a 16-Core 5+ GHz DCM.
ISSCC
Ofer Geva, Christopher J. Berry, Robert J. Sonnelitter, David Wolpert, Adam Collura, Thomas Strach, Di Phan, Cédric Lichtenau, Alper Buyuktosunoglu, Hubert Harrer, Jeffrey A. Zitz, Chad Marquart, Douglas Malone, Tobias Webel, Adam Jatkowski, John Isakson, Dina Hamid, Mark Cichanowski, Michael Romain, Faisal Hasan, Kevin Williams, Jesse Surprise, Chris Cavitt, Mark Cohen
2015 J jnl
Electronic packaging of the IBM z13 processor drawer.
IBM J. Res. Dev.
Wiren Dale Becker, Hubert Harrer, Andreas Huber, W. L. Brodsky, R. Krabbenhoft, M. A. Cracraft, Dierk Kaller, Gregory R. Edlund, Thomas Strach
2014 J jnl
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.
IEEE J. Solid State Circuits
James D. Warnock, Yuen H. Chan, Hubert Harrer, Sean M. Carey, Gerard Salem, Doug Malone, Ruchir Puri, Jeffrey A. Zitz, Adam Jatkowski, Gerald Strevig, Ayan Datta, Anne Gattiker, Aditya Bansal, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, David L. Rude, Leon J. Sigal, Thomas Strach, Howard H. Smith, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb
2013 — conf
5.5GHz system z microprocessor and multi-chip module.
ISSCC
James D. Warnock, Yuen H. Chan, Hubert Harrer, David L. Rude, Ruchir Puri, Sean M. Carey, Gerard Salem, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, Adam Jatkowski, Gerald Strevig, Leon J. Sigal, Ayan Datta, Anne Gattiker, Aditya Bansal, Doug Malone, Thomas Strach, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb
2012 J jnl
Electronic packaging of the IBM System z196 enterprise-class server processor cage.
IBM J. Res. Dev.
Thomas Strach, Frank E. Bosco, Kenneth L. Christian, Kevin R. Covi, Martin Eckert, Gregory R. Edlund, Roland Frech, Hubert Harrer, Andreas Huber, Dierk Kaller, Martin Kindscher, A. Z. Muszynski, G. A. Peterson, Claudio Siviero, Jochen Supper, Otto A. Torreiter, Thomas-Michael Winkel
2009 J jnl
Packaging design challenges of the IBM System z10 Enterprise Class server.
IBM J. Res. Dev.
Thomas-Michael Winkel, Hubert Harrer, Dierk Kaller, Jochen Supper, Daniel M. Dreps, Kenneth L. Christian, D. Cosmadelis, Tingdong Zhou, Thomas Strach, J. Ludwig, David L. Edwards
2007 J jnl
High-speed interconnect and packaging design of the IBM System z9 processor cage.
IBM J. Res. Dev.
Hubert Harrer, Daniel M. Dreps, Thomas-Michael Winkel, Wolfgang Scholz, Bao G. Truong, Andreas Huber, Tingdong Zhou, Kenneth L. Christian, Gary F. Goth
2004 J jnl
First- and second-level packaging of the z990 processor cage.
IBM J. Res. Dev.
Thomas-Michael Winkel, Wiren Dale Becker, Hubert Harrer, Harald Pross, Dierk Kaller, Bernd Garben, Bruce J. Chamberlin, Scott A. Kuppinger
2002 J jnl
First- and second-level packaging for the IBM eServer z900.
IBM J. Res. Dev.
Hubert Harrer, Harald Pross, Thomas-Michael Winkel, Wiren Dale Becker, Herb I. Stoller, Masakazu Yamamoto, Shinji Abe, Bruce J. Chamberlin, George A. Katopis
1994 C conf
A Current-Mode DTCNN Universal Chip .
ISCAS
Hubert Harrer, Josef A. Nossek, Tamás Roska, Leon O. Chua
1993 J jnl
On the convergence of discrete-time neural networks.
Int. J. Circuit Theory Appl.
Hubert Harrer, Zbigniew Galias, Josef A. Nossek
1992 J jnl
An analog implementation of discrete-time cellular neural networks.
IEEE Trans. Neural Networks
Hubert Harrer, Josef A. Nossek, Rudolf Stelzl
1992 — —
Discrete time cellular neural networks.
Hubert Harrer
1992 J jnl
Discrete-time cellular neural networks.
Int. J. Circuit Theory Appl.
Hubert Harrer, Josef A. Nossek