Huawei Li - RankMe

379 papers A* 27A 47B 10C 17Misc 20Journal 163Unranked 95

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	AssertMiner: Module-Level Spec Generation and Assertion Mining using Static Analysis Guided LLMs. ASP-DAC Hongqin Lyu, Yonghao Wang, Jiaxin Zhou, Zhiteng Chao, Tiancheng Wang, Huawei Li
2026	J	`jnl`	Chipletizer 2.0: Toward Cost-Effective Chiplet Design via Reuse-Aware Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fuping Li, Ding Yuan, Yujie Wang, Juelei Zhou, Xihao Liang, Yinhe Han, Huawei Li, Xiaowei Li, Ying Wang
2026	J	`jnl`	From Buffers to Registers: Unlocking Fine-Grained FlashAttention with Hybrid-Bonded 3D NPU Co-Design. CoRR Jinxin Yu, Yudong Pan, Mengdi Wang, Huawei Li, Yinhe Han, Xiaowei Li, Ying Wang
2026	J	`jnl`	Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided Verification. CoRR Yonghao Wang, Jiaxin Zhou, Yang Yin, Hongqin Lyu, Zhiteng Chao, Wenchao Ding, Jing Ye, Tiancheng Wang, Huawei Li
2026	J	`jnl`	Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures. CoRR Zizhen Liu, Fangzhiyi Wang, Mengdi Wang, Jing Ye, Hayden Kwok-Hay So, Cheng Liu, Huawei Li
2026	J	`jnl`	On the Vulnerability of FHE Computation to Silent Data Corruption. CoRR Jianan Mu, Ge Yu, Zhaoxuan Kan, Song Bian, Liang Kong, Zizhen Liu, Cheng Liu, Jing Ye, Huawei Li
2026	J	`jnl`	Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction. CoRR Jiaping Tang, Jianan Mu, TianYun Ma, Zhiteng Chao, Jing Ye, Huawei Li
2026	J	`jnl`	RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning. CoRR Xinyu Zhang, Zhiteng Chao, Yonghao Wang, Bin Sun, TianYun Ma, Tianmeng Yang, Jianan Mu, Jing Justin Ye, Huawei Li
2026	J	`jnl`	Twins: Hardware Similarity Evaluation Framework Using Graph Neural Network. ACM Trans. Design Autom. Electr. Syst. Yiran He, Haihua Shen, Zirui Jiang, Shan Li, Xiao Ji, Huawei Li
2025	C	`conf`	A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs. ISCAS Peng Dang, Huawei Li, Wei Wang
2025	J	`jnl`	A data-centric chip design agent framework for Verilog code generation. ACM Trans. Design Autom. Electr. Syst. Kaiyan Chang, Wenlong Zhu, Kun Wang, Xinyang He, Nan Yang, Zhirong Chen, Dantong Jin, Cangyuan Li, Yunhao Zhou, Hao Yan, Zhuoliang Zhao, Yuan Cheng, Mengdi Wang, Shengwen Liang, Yinhe Han, Xiaowei Li, Huawei Li, Ying Wang
2025	J	`jnl`	A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow. Integr. Zhiteng Chao, Xindi Zhang, JunYing Huang, Zizhen Liu, Yixuan Zhao, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li
2025	J	`jnl`	APoX-M: Accelerate deep point cloud analysis via adaptive graph construction. Integr. Lei Dai, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li
2025	A	`conf`	An Efficient Parallel Fault Simulator for Functional Patterns on Multi-Core Systems. DATE Xiaoze Lin, Liyang Lai, Huawei Li, Biwei Xie, Xingquan Li
2025	J	`jnl`	AssertFix: Empowering Automated Assertion Fix via Large Language Models. CoRR Hongqin Lyu, Yunlin Du, Yonghao Wang, Zhiteng Chao, Tiancheng Wang, Huawei Li
2025	—	`conf`	AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging. ATS Hongqin Lyu, Yonghao Wang, Yunlin Du, Mingyu Shi, Zhiteng Chao, Wenxing Li, Tiancheng Wang, Huawei Li
2025	J	`jnl`	AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging. CoRR Hongqin Lyu, Yonghao Wang, Yunlin Du, Mingyu Shi, Zhiteng Chao, Wenxing Li, Tiancheng Wang, Huawei Li
2025	J	`jnl`	AssertMiner: Module-Level Spec Generation and Assertion Mining using Static Analysis Guided LLMs. CoRR Hongqin Lyu, Yonghao Wang, Jiaxin Zhou, Zhiteng Chao, Tiancheng Wang, Huawei Li
2025	J	`jnl`	AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models. ACM Trans. Design Autom. Electr. Syst. Cangyuan Li, Chujie Chen, Yudong Pan, Wenjun Xu, Yiqi Liu, Kaiyan Chang, Yujie Wang, Mengdi Wang, Huawei Li, Yinhe Han, Ying Wang
2025	J	`jnl`	BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction. CoRR Liwei Ni, Jiaxi Zhang, Shenggen Zheng, Junfeng Liu, Xingyu Meng, Biwei Xie, Xingquan Li, Huawei Li
2025	A*	`conf`	Bridging Layout and RTL: Knowledge Distillation based Timing Prediction. ICML Mingjun Wang, Yihan Wen, Bin Sun, Jianan Mu, Juan Li, Xiaoyi Wang, Jing Justin Ye, Bei Yu, Huawei Li
2025	A	`conf`	DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs. SC Mingkai Chen, Tianhua Han, Cheng Liu, Shengwen Liang, Kuai Yu, Lei Dai, Ziming Yuan, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li
2025	J	`jnl`	DeepAssert: An LLM-Aided Verification Framework with Fine-Grained Assertion Generation for Modules with Extracted Module Specifications. CoRR Yonghao Wang, Jiaxin Zhou, Hongqin Lyu, Zhiteng Chao, Tiancheng Wang, Huawei Li
2025	A*	`conf`	EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components. DAC Mingjun Wang, Hui Wang, Jianan Mu, Xinyu Zhang, Bin Sun, Yihan Wen, Zizhen Liu, Feng Gu, Jun Gao, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li
2025	A	`conf`	ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. DATE Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2025	J	`jnl`	ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. CoRR Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shenwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2025	—	`conf`	ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. ASP-DAC Mingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li, Jing Ye, Xiaowei Li
2025	J	`jnl`	Extend IVerilog to Support Batch RTL Fault Simulation. CoRR Jiaping Tang, Jianan Mu, Zizhen Liu, Zhiteng Chao, Jing Ye, Huawei Li
2025	J	`jnl`	FUS: FPGA-based Universal Sketch with homogeneous and heterogeneous memory architectures. CCF Trans. High Perform. Comput. Yunkun Liao, Jingya Wu, Wenyan Lu, Huawei Li, Xiaowei Li, Guihai Yan
2025	J	`jnl`	Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware. CoRR Jianan Mu, Mingyu Shi, Yining Wang, Tianmeng Yang, Bin Sun, Xing Hu, Jing Ye, Huawei Li
2025	J	`jnl`	From Large to Small: Transferring CUDA Optimization Expertise via Reasoning Graph. CoRR Junfeng Gong, Zhiyi Wei, Junying Chen, Cheng Liu, Huawei Li
2025	A*	`conf`	FrontOrder: Frontier-Guided Graph Reordering. ICDE Xinmiao Zhang, Cheng Liu, Shengwen Liang, Chenwei Xiong, Yu Zhang, Lei Zhang, Huawei Li, Xiaowei Li
2025	B	`conf`	Frontier-guided Graph Reordering. PPoPP Xinmiao Zhang, Cheng Liu, Shengwen Liang, Chenwei Xiong, Yu Zhang, Lei Zhang, Huawei Li, Xiaowei Li
2025	J	`jnl`	Functional Testing and Repair for ReRAM-Based Deep-Learning Accelerators. IEEE Des. Test Wen Li, Ying Wang, Huawei Li, Xiaowei Li, Kaiwei Zou
2025	Misc	`conf`	HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion. VTS Zhiteng Chao, Bin Sun, Hongqin Lyu, Ge Yu, Minjun Wang, Wenxing Li, Zizhen Liu, Jianan Mu, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li
2025	J	`jnl`	InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning. CoRR Bin Sun, Rengang Zhang, Zhiteng Chao, Zizhen Liu, Jianan Mu, Jing Ye, Huawei Li
2025	A*	`conf`	LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow. MICRO Kaiyan Chang, Wenlong Zhu, Shengwen Liang, Huawei Li, Ying Wang
2025	J	`jnl`	LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow. CoRR Kaiyan Chang, Wenlong Zhu, Shengwen Liang, Huawei Li, Ying Wang
2025	J	`jnl`	Large Processor Chip Model. CoRR Kaiyan Chang, Mingzhi Chen, Yunji Chen, Zhirong Chen, Dongrui Fan, Junfeng Gong, Nan Guo, Yinhe Han, Qinfen Hao, Shuo Hou, Xuanjing Huang, Pengwei Jin, Changxin Ke, Cangyuan Li, Guangli Li, Huawei Li, Kuan Li, Naipeng Li, Shengwen Liang, Cheng Liu, Hongwei Liu, Jiahua Liu, Junliang Lv, Jianan Mu, Jin Qin, Bin Sun, Chenxi Wang, Duo Wang, Mingjun Wang, Ying Wang, Chenggang Wu, Peiyang Wu, Teng Wu, Xiao Xiao, Mengyao Xie, Chenwei Xiong, Ruiyuan Xu, Mingyu Yan, Xiaochun Ye, Kuai Yu, Rui Zhang, Shuoming Zhang, Jiacheng Zhao
2025	A*	`conf`	MOSS: Multi-Modal Representation Learning on Sequential Circuits. DAC Mingjun Wang, Bin Sun, Jianan Mu, Feng Gu, Boyu Han, Tianmeng Yang, Xinyu Zhang, Silin Liu, Yihan Wen, Hui Wang, Jun Gao, Zhiteng Chao, Husheng Han, Zizhen Liu, Shengwen Liang, Jing Ye, Bei Yu, Xiaowei Li, Huawei Li
2025	J	`jnl`	Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation. ACM Trans. Design Autom. Electr. Syst. Zhiteng Chao, Feng Gu, JunYing Huang, Wenjie Li, Jing Ye, Huawei Li, Xiaowei Li
2025	A*	`conf`	NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search. HPCA Ziming Yuan, Lei Dai, Wen Li, Jie Zhang, Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li, Jiafeng Guo, Peng Wang, Renhai Chen, Gong Zhang
2025	J	`jnl`	OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine-Learning Tasks in Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Liwei Ni, Rui Wang, Miao Liu, Xingyu Meng, Xiaoze Lin, Junfeng Liu, Guojie Luo, Zhufei Chu, Weikang Qian, Xiaoyan Yang, Biwei Xie, Xingquan Li, Huawei Li
2025	J	`jnl`	Oxpecker: Leaking Secrets via Fetch Target Queue. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shan Li, Zheliang Xu, Haihua Shen, Huawei Li
2025	—	`conf`	PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System. ASPLOS (2) Yintao He, Haiyu Mao, Christina Giannoula, Mohammad Sadrosadati, Juan Gómez-Luna, Huawei Li, Xiaowei Li, Ying Wang, Onur Mutlu
2025	J	`jnl`	PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System. CoRR Yintao He, Haiyu Mao, Christina Giannoula, Mohammad Sadrosadati, Juan Gómez-Luna, Huawei Li, Xiaowei Li, Ying Wang, Onur Mutlu
2025	J	`jnl`	ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction. CoRR Bin Sun, Jingyi Zhou, Jianan Mu, Zhiteng Chao, Tianmeng Yang, Ziyue Xu, Jing Ye, Huawei Li
2025	A*	`conf`	PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT. DAC Zhiteng Chao, Xindi Zhang, Xinyu Zhang, Jianan Mu, Zizhen Liu, Shengwen Liang, Shaowei Cai, Jing Ye, Xiaowei Li, Huawei Li
2025	A	`conf`	RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule. ICCAD Jiaping Tang, Jianan Mu, Zizhen Liu, Ge Yu, Tenghui Hua, Bin Sun, Silin Liu, Jing Ye, Huawei Li
2025	J	`jnl`	RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule. CoRR Jiaping Tang, Jianan Mu, Zizhen Liu, Ge Yu, Tenghui Hua, Bin Sun, Silin Liu, Jing Ye, Huawei Li
2025	A	`conf`	RTPU: Unifying Non-Private and Private Inference with Reconfigurable Architecture. ICCAD Fuping Li, Ying Wang, Yinghao Yang, Jingxuan Li, Yibo Du, Huawei Li, Yinhe Han, Hang Lu, Xiaowei Li
2025	A	`conf`	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration. ITC Zhiteng Chao, Rengang Zhang, Feng Gu, Hongqin Lyu, Bin Sun, Wenxing Li, Zizhen Liu, Jianan Mu, Jing Ye, Xiaowei Li, Huawei Li
2025	A	`conf`	Taijigraph: an Out-Of-Core Graph Processing System Enhanced with Computational Storage. IPDPS Xinmiao Zhang, Cheng Liu, Shengwen Liang, Hayden Kwok-Hay So, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li
2025	J	`jnl`	Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT. CoRR Zhiteng Chao, Yonghao Wang, Xinyu Zhang, Jiaxin Zhou, Tenghui Hua, Husheng Han, Tianmeng Yang, Jianan Mu, Bei Yu, Rui Zhang, Jing Ye, Huawei Li
2025	J	`jnl`	Understanding and Mitigating Errors of LLM-Generated RTL Code. CoRR Jiazheng Zhang, Cheng Liu, Huawei Li
2025	A	`conf`	VIRTUAL: Vector-based Dynamic Power Estimation via Decoupled Multi-Modality Learning. ICCAD Yuntao Lu, Mingjun Wang, Yihan Wen, Boyu Han, Jianan Mu, Huawei Li, Bei Yu
2024	B	`conf`	A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. ASPDAC Zhiteng Chao, Xindi Zhang, JunYing Huang, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li
2024	J	`jnl`	A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs. CoRR Peng Dang, Huawei Li, Wei Wang
2024	B	`conf`	A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256. ETS Han Yan, Shuai Chen, JunYing Huang, Jing Ye, Huawei Li, Xiaowei Li
2024	—	`conf`	A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification. ITC-Asia Zhiteng Chao, Qinluan Dai, Jiale Li, Zizhen Liu, Wenxing Li, Hongqin Lyu, Jing Ye, Huawei Li, Xiaowei Li
2024	J	`jnl`	A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yintao He, Bing Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
2024	A	`conf`	AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search. ICCAD Lei Dai, Ziming Yuan, Wen Li, Shengwen Liang, Kaiwei Zou, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
2024	B	`conf`	APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction. ASPDAC Lei Dai, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li
2024	—	`conf`	Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction. ATS Jiaping Tang, Zizhen Liu, Jianan Mu, Feng Gu, Mingjun Wang, Wenxing Li, Jing Ye, Xiaowei Li, Huawei Li
2024	A*	`conf`	Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. DAC Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li
2024	J	`jnl`	An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lian Liu, Ying Wang, Xiandong Zhao, Weiwei Chen, Huawei Li, Xiaowei Li, Yinhe Han
2024	J	`jnl`	An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mingkai Chen, Cheng Liu, Shengwen Liang, Lei He, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li
2024	J	`jnl`	ApproxPilot: A GNN-based Accelerator Approximation Framework. CoRR Qing Zhang, Cheng Liu, Siting Liu, Yajuan Hui, Huawei Li, Xiaowei Li
2024	—	`conf`	Athena: Add More Intelligence to RMT-Based Network Data Plane with Low-Bit Quantization. Euro-Par (2) Yunkun Liao, Hanyue Lin, Jingya Wu, Wenyan Lu, Huawei Li, Xiaowei Li, Guihai Yan
2024	A	`conf`	Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture. DATE Yintao He, Shixin Zhao, Songyun Qu, Huawei Li, Xiaowei Li, Ying Wang
2024	J	`jnl`	Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Network. CoRR Liwei Ni, Xinquan Li, Biwei Xie, Huawei Li
2024	B	`conf`	Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. ASPDAC Fuping Li, Ying Wang, Yujie Wang, Mengdi Wang, Yinhe Han, Huawei Li, Xiaowei Li
2024	A*	`conf`	Chiplever: Towards Effortless Extension of Chiplet-based System for FHE. DAC Yibo Du, Ying Wang, Bing Li, Fuping Li, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han
2024	A	`conf`	DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. ICCAD Feng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye, Huawei Li, Xiaowei Li
2024	J	`jnl`	DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs. CoRR Mingkai Chen, Tianhua Han, Cheng Liu, Shengwen Liang, Kuai Yu, Lei Dai, Ziming Yuan, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li
2024	A*	`conf`	Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. DAC Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2024	J	`jnl`	Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. CoRR Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2024	A*	`conf`	Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. DAC Lian Liu, Zhaohui Xu, Yintao He, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han
2024	—	`conf`	Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262. ITC-Asia Mingjun Wang, Hui Wang, Jianan Mu, Zizhen Liu, Jun Gao, Jing Ye, Huawei Li, Xiaowei Li
2024	A	`conf`	GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. DATE Yibo Du, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han
2024	J	`jnl`	Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation. CoRR Xinmiao Zhang, Zheng Feng, Shengwen Liang, Xinyu Chen, Cheng Liu, Huawei Li, Xiaowei Li
2024	A	`conf`	HLSPilot: LLM-based High-Level Synthesis. ICCAD Chenwei Xiong, Cheng Liu, Huawei Li, Xiaowei Li
2024	J	`jnl`	HLSPilot: LLM-based High-Level Synthesis. CoRR Chenwei Xiong, Cheng Liu, Huawei Li, Xiaowei Li
2024	A	`conf`	HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System. DATE Shengwen Liang, Ziming Yuan, Ying Wang, Dawen Xu, Huawei Li, Xiaowei Li
2024	J	`jnl`	IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA. CoRR Zesong Jiang, Qing Zhang, Cheng Liu, Huawei Li, Xiaowei Li
2024	J	`jnl`	MCU-MixQ: A HW/SW Co-optimized Mixed-precision Neural Network Design Framework for MCUs. CoRR Junfeng Gong, Cheng Liu, Long Cheng, Huawei Li, Xiaowei Li
2024	J	`jnl`	MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing. IEEE Trans. Very Large Scale Integr. Syst. Haitong Huang, Cheng Liu, Xinghua Xue, Bo Liu, Huawei Li, Xiaowei Li
2024	A	`conf`	Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. ICCAD Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang
2024	J	`jnl`	Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. CoRR Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang
2024	J	`jnl`	On Modeling and Detecting Trojans in Instruction Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Zhang, Aodi He, Jiaying Li, Ahmed Rezine, Zebo Peng, Erik Larsson, Tao Yang, Jianhui Jiang, Huawei Li
2024	J	`jnl`	OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis. CoRR Liwei Ni, Rui Wang, Miao Liu, Xingyu Meng, Xiaoze Lin, Junfeng Liu, Guojie Luo, Zhufei Chu, Weikang Qian, Xiaoyan Yang, Biwei Xie, Xingquan Li, Huawei Li
2024	J	`jnl`	PDG: A Prefetcher for Dynamic Graph Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xinmiao Zhang, Cheng Liu, Jiacheng Ni, Yuanqing Cheng, Lei Zhang, Huawei Li, Xiaowei Li
2024	J	`jnl`	Parallel Static Learning Toward Heterogeneous Computing Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaoze Lin, Liyang Lai, Huawei Li
2024	J	`jnl`	SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks. IEEE Trans. Inf. Forensics Secur. Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li
2024	J	`jnl`	SigDLA: A Deep Learning Accelerator Extension for Signal Processing. CoRR Fangfa Fu, Wenyu Zhang, Zesong Jiang, Zhiyu Zhu, Guoyu Li, Bing Yang, Cheng Liu, Liyi Xiao, Jinxiang Wang, Huawei Li, Xiaowei Li
2024	A*	`conf`	SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning. DAC Wenxing Li, Hongqin Lyu, Shengwen Liang, Tiancheng Wang, Huawei Li
2024	B	`conf`	iEDA: An Open-source infrastructure of EDA. ASPDAC Xingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang, Chunan Zhuang, Hao Wang, Yifan Li, Yihang Qiu, Guojie Luo, Huawei Li, Haihua Shen, Mingyu Chen, Dongbo Bu, Wenxing Zhu, Ye Cai, Xiaoming Xiong, Ying Jiang, Yi Heng, Peng Zhang, Bei Yu, Biwei Xie, Yungang Bao
2023	—	`conf`	A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT. ATS Zhiteng Chao, Senlin Wang, Pengyu Tian, Shuwen Yuan, Huawei Li, Jing Ye, Xiaowei Li
2023	—	`conf`	A Template Attack on Reduction Without Reference Device on Kyber. ATS Yipei Yang, JunYing Huang, Zongyue Wang, Jing Ye, Zihao Sun, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao
2023	A*	`conf`	APPEND: Rethinking ASIP Synthesis in the Era of AI. DAC Cangyuan Li, Ying Wang, Huawei Li, Yinhe Han
2023	J	`jnl`	Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. ACM Trans. Design Autom. Electr. Syst. Cheng Chu, Cheng Liu, Dawen Xu, Ying Wang, Tao Luo, Huawei Li, Xiaowei Li
2023	C	`conf`	Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. ICCD Liwei Ni, Zonglin Yang, Jiaxi Zhang, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li
2023	J	`jnl`	Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. CoRR Liwei Ni, Zonglin Yang, Jiaxi Zhang, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li
2023	—	`conf`	Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors. ATS Wen Li, Ying Wang, Kaiwei Zou, Huawei Li, Xiaowei Li
2023	J	`jnl`	ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers. CoRR Xinghua Xue, Cheng Liu, Haitong Huang, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li
2023	C	`conf`	BGNN-HT: Bidirectional Graph Neural Network for Hardware Trojan Cells Detection at Gate Level. ISCAS Peiheng Zhan, Haihua Shen, Shan Li, Huawei Li
2023	J	`jnl`	ChipGPT: How far are we from natural language hardware design. CoRR Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2023	J	`jnl`	Chosen ciphertext correlation power analysis on Kyber. Integr. Yipei Yang, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao
2023	B	`conf`	Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators. ICPADS Kaiwei Zou, Songyun Qu, Wen Li, Ying Wang, Huawei Li, Yongpan Liu
2023	—	`conf`	Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design. ATS Jianan Mu, Huajie Tan, Shuai Chen, Min Cai, Jing Ye, Huawei Li, Xiaowei Li
2023	J	`jnl`	Cross-Layer Optimization for Fault-Tolerant Deep Learning. CoRR Qing Zhang, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Huawei Li, Xiaowei Li
2023	J	`jnl`	DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning. J. Supercomput. Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2023	A	`conf`	DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. ICCAD Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yang, Ying Wang, Huawei Li, Xiaowei Li
2023	J	`jnl`	DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. CoRR Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yang, Ying Wang, Huawei Li, Xiaowei Li
2023	A	`conf`	Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. DATE Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2023	J	`jnl`	Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. IEEE Trans. Very Large Scale Integr. Syst. Xinghua Xue, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li
2023	J	`jnl`	Exploring Winograd Convolution for Cost-effective Neural Network Fault Tolerance. CoRR Xinghua Xue, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li
2023	A	`conf`	Fast Exact NPN Classification with Influence-Aided Canonical Form. ICCAD Yonghe Zhang, Liwei Ni, Jiaxi Zhang, Guojie Luo, Huawei Li, Shenggen Zheng
2023	J	`jnl`	Fast Exact NPN Classification with Influence-aided Canonical Form. CoRR Yonghe Zhang, Liwei Ni, Jiaxi Zhang, Guojie Luo, Huawei Li, Shenggen Zheng
2023	—	`conf`	Intelligent Automatic Test Pattern Generation for Digital Circuits Based on Reinforcement Learning. ATS Wenxing Li, Hongqin Lyu, Shengwen Liang, Tiancheng Wang, Pengyu Tian, Huawei Li
2023	J	`jnl`	MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA. CoRR Liwei Ni, Zonglin Yang, Jiaxi Zhang, Changhong Feng, Jianhua Liu, Guojie Luo, Huawei Li, Biwei Xie, Xingquan Li
2023	J	`jnl`	MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing. CoRR Haitong Huang, Cheng Liu, Xinghua Xue, Ying Wang, Huawei Li, Xiaowei Li
2023	—	`conf`	Message from the Chairs. ATS Huawei Li, Jing Ye, Wei Hu, Jiliang Zhang
2023	J	`jnl`	On-Line Fault Protection for ReRAM-Based Neural Networks. IEEE Trans. Computers Wen Li, Ying Wang, Cheng Liu, Yintao He, Lian Liu, Huawei Li, Xiaowei Li
2023	B	`conf`	Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants. ETS Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li
2023	C	`conf`	PANG: A Pattern-Aware GCN Accelerator for Universal Graphs. ICCD Yibo Du, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han
2023	J	`jnl`	Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip. J. Comput. Sci. Technol. Ying Zhang, Pengfei Ji, Pan-Wei Zhu, Zebo Peng, Huawei Li, Jian-Hui Jiang
2023	J	`jnl`	Preface. J. Comput. Sci. Technol. Weikang Qian, Ke Chen, Wei-Qiang Liu, Huawei Li
2023	J	`jnl`	Reliability Analysis of Vision Transformers. CoRR Xinghua Xue, Cheng Liu, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li
2023	A	`conf`	Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. DATE Jiaxi Zhang, Shenggen Zheng, Liwei Ni, Huawei Li, Guojie Luo
2023	J	`jnl`	Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. CoRR Jiaxi Zhang, Shenggen Zheng, Liwei Ni, Huawei Li, Guojie Luo
2023	J	`jnl`	SPFL: A Self-purified Federated Learning Method Against Poisoning Attacks. CoRR Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li
2023	J	`jnl`	Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li
2023	J	`jnl`	Soft Error Reliability Analysis of Vision Transformers. IEEE Trans. Very Large Scale Integr. Syst. Xinghua Xue, Cheng Liu, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li
2023	J	`jnl`	Statistical Modeling of Soft Error Influence on Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haitong Huang, Xinghua Xue, Cheng Liu, Ying Wang, Tao Luo, Long Cheng, Huawei Li, Xiaowei Li
2023	J	`jnl`	iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Library. CoRR Xingquan Li, Simin Tao, Zengrong Huang, Shijian Chen, Zhisheng Zeng, Liwei Ni, Zhipeng Huang, Chunan Zhuang, Hongxi Wu, Weiguo Li, Xueyan Zhao, He Liu, Shuaiying Long, Wei He, Bojun Liu, Sifeng Gan, Zihao Yu, Tong Liu, Yuchi Miao, Zhiyuan Yan, Hao Wang, Jie Zhao, Yifan Li, Ruizhi Liu, Xiaoze Lin, Bo Yang, Zhen Xue, Fuxing Huang, Zonglin Yang, Zhenggang Wu, Jiangkao Li, Yuezuo Liu, Ming Peng, Yihang Qiu, Wenrui Wu, Zheqing Shao, Kai Mo, Jikang Liu, Yuyao Liang, Mingzhe Zhang, Zhuang Ma, Xiang Cong, Daxiang Huang, Guojie Luo, Huawei Li, Haihua Shen, Mingyu Chen, Dongbo Bu, Wenxing Zhu, Ye Cai, Xiaoming Xiong, Ying Jiang, Yi Heng, Peng Zhang, Biwei Xie, Yungang Bao
2022	J	`jnl`	A Fast Precision Tuning Solution for Always-On DNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Yintao He, Long Cheng, Huawei Li, Xiaowei Li
2022	—	`conf`	A Hardware Trojan Trigger Localization Method in RTL based on Control Flow Features. ATS Hao Huang, Haihua Shen, Shan Li, Huawei Li
2022	—	`conf`	A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber. ASP-DAC Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao
2022	J	`jnl`	An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yongchen Wang, Ying Wang, Huawei Li, Xiaowei Li
2022	J	`jnl`	BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature. IEEE Trans. Very Large Scale Integr. Syst. Ying Zhang, Yi Ding, Zebo Peng, Huawei Li, Masahiro Fujita, Jianhui Jiang
2022	J	`jnl`	CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures. IEEE Trans. Computers Kaiwei Zou, Ying Wang, Long Cheng, Songyun Qu, Huawei Li, Xiaowei Li
2022	J	`jnl`	Cognitive SSD+: a deep learning engine for energy-efficient unstructured data retrieval. CCF Trans. High Perform. Comput. Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li
2022	J	`jnl`	DHSA: Efficient Doubly Homomorphic Secure Aggregation for Cross-silo Federated Learning. CoRR Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2022	—	`conf`	Exploring the high-throughput and low-delay hardware design of SM4 on FPGA. ISOCC Yixiao Chen, Jinfeng Song, Shuai Chen, Yuan Cao, Jing Ye, Huawei Li, Xiaowei Li, Xin Lou, Enyi Yao
2022	J	`jnl`	Fault-Tolerant Deep Learning: A Hierarchical Perspective. CoRR Cheng Liu, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li
2022	A	`conf`	GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. ICCAD Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li
2022	J	`jnl`	HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cheng Liu, Cheng Chu, Dawen Xu, Ying Wang, Qianlong Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng
2022	A*	`conf`	InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs. DAC Yintao He, Songyun Qu, Ying Wang, Bing Li, Huawei Li, Xiaowei Li
2022	A	`conf`	NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network. DATE Fuping Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
2022	C	`conf`	Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance. ICCD Lei Dai, Ying Wang, Cheng Liu, Fuping Li, Huawei Li, Xiaowei Li
2022	A	`conf`	SASH: Efficient secure aggregation based on SHPRG for federated learning. UAI Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2022	J	`jnl`	SATAM: A SAT Attack Resistant Active Metering Against IC Overbuilding. IEEE Trans. Emerg. Top. Comput. Aijiao Cui, Zhen Weng, Hui Zhang, Gang Qu, Huawei Li
2022	J	`jnl`	Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yintao He, Ying Wang, Huawei Li, Xiaowei Li
2022	Misc	`conf`	Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective. VTS Cheng Liu, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li
2022	J	`jnl`	Statistical Modeling of Soft Error Influence on Neural Networks. CoRR Haitong Huang, Xinghua Xue, Cheng Liu, Ying Wang, Tao Luo, Long Cheng, Huawei Li, Xiaowei Li
2022	J	`jnl`	Taming Process Variations in CNFET for Efficient Last-Level Cache Design. IEEE Trans. Very Large Scale Integr. Syst. Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Huawei Li, Xiaowei Li
2022	A*	`conf`	VStore: in-storage graph based vector search accelerator. DAC Shengwen Liang, Ying Wang, Ziming Yuan, Cheng Liu, Huawei Li, Xiaowei Li
2021	J	`jnl`	An Edge 3D CNN Accelerator for Low-Power Activity Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Yongchen Wang, Cong Shi, Long Cheng, Huawei Li, Xiaowei Li
2021	J	`jnl`	Editorial for the special issue on reliability and power efficiency for HPC. CCF Trans. High Perform. Comput. Jifeng He, Chenggang Wu, Huawei Li, Yang Guo, Tao Li
2021	J	`jnl`	Efficient Secure Aggregation Based on SHPRG For Federated Learning. CoRR Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2021	J	`jnl`	EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks. IEEE Trans. Computers Shengwen Liang, Ying Wang, Cheng Liu, Lei He, Huawei Li, Dawen Xu, Xiaowei Li
2021	J	`jnl`	Energy-Efficient Accelerator Design for Deformable Convolution Networks. CoRR Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng
2021	A*	`conf`	GCiM: A Near-Data Processing Accelerator for Graph Construction. DAC Lei He, Cheng Liu, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li
2021	—	`conf`	GLIST: Towards In-Storage Graph Learning. USENIX ATC Cangyuan Li, Ying Wang, Cheng Liu, Shengwen Liang, Huawei Li, Xiaowei Li
2021	J	`jnl`	HyCA: A Hybrid Computing Architecture for Fault Tolerant Deep Learning. CoRR Dawen Xu, Qianlong Wang, Cheng Liu, Cheng Chu, Ying Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng
2021	A*	`conf`	PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams. DAC Yongchen Wang, Ying Wang, Huawei Li, Xiaowei Li
2021	J	`jnl`	Preface. J. Comput. Sci. Technol. Huawei Li
2021	J	`jnl`	R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors. IEEE Trans. Very Large Scale Integr. Syst. Dawen Xu, Meng He, Cheng Liu, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, Kwang-Ting Cheng
2021	J	`jnl`	R2F: A Remote Retraining Framework for AIoT Processors with Computing Errors. CoRR Dawen Xu, Meng He, Cheng Liu, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, Kwang-Ting Cheng
2021	J	`jnl`	Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System. IEEE Trans. Very Large Scale Integr. Syst. Dawen Xu, Ziyang Zhu, Cheng Liu, Ying Wang, Shuang Zhao, Lei Zhang, Huaguo Liang, Huawei Li, Kwang-Ting Cheng
2021	—	`conf`	Scalable Parallel Static Learning. ITC-Asia Xiaoze Lin, Liyang Lai, Huawei Li
2021	—	`conf`	SeGa: A Trojan Detection Method Combined With Gate Semantics. ATS Yunying Ye, Shan Li, Haihua Shen, Huawei Li, Xiaowei Li
2021	Misc	`conf`	Special Session - Test for AI Chips: from DFT to On-line Testing. VTS Huawei Li, Xiaowei Li, Yu Huang, Ying Wang, Gary Guo
2021	A*	`conf`	TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. DAC Yintao He, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
2021	J	`jnl`	Taming Process Variations in CNFET for Efficient Last Level Cache Design. CoRR Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Yuanqing Cheng, Huawei Li, Xiaowei Li
2021	J	`jnl`	To cloud or not to cloud: an on-line scheduler for dynamic privacy-protection of deep learning workload on edge devices. CCF Trans. High Perform. Comput. Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li
2020	J	`jnl`	A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li
2020	A	`conf`	A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning. ICCAD Ying Wang, Mengdi Wang, Bing Li, Huawei Li, Xiaowei Li
2020	Misc	`conf`	A New Secure Scan Design with PUF-based Key for Authentication. VTS Qidong Wang, Aijiao Cui, Gang Qu, Huawei Li
2020	A*	`conf`	An Efficient Deep Learning Accelerator for Compressed Video Analysis. DAC Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li
2020	J	`jnl`	Architecting Effectual Computation for Machine Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hang Lu, Mingzhe Zhang, Yinhe Han, Qi Wang, Huawei Li, Xiaowei Li
2020	A	`conf`	CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding. DATE Dawen Xu, Kexin Chu, Cheng Liu, Ying Wang, Lei Zhang, Huawei Li
2020	A	`conf`	DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. ICCAD Shengwen Liang, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li
2020	J	`jnl`	Evaluating and Constraining Hardware Assertions with Absent Scenarios. J. Comput. Sci. Technol. Huina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, Xiaowei Li
2020	J	`jnl`	GPGPU-Based ATPG System: Myth or Reality? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Liyang Lai, Kun-Han Tsai, Huawei Li
2020	A	`conf`	HIT: A Hidden Instruction Trojan Model for Processors. DATE Jiaqi Zhang, Ying Zhang, Huawei Li, Jianhui Jiang
2020	—	`conf`	Multi-task Scheduling for PIM-based Heterogeneous Computing System. ACM Great Lakes Symposium on VLSI Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Xianzhong Zhou, Lei Zhang, Huaguo Liang, Huawei Li
2020	J	`jnl`	MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection. IEEE Access Qingli Guo, Jing Ye, Yu Hu, Guohe Zhang, Xiaowei Li, Huawei Li
2020	—	`conf`	Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER. ATS Yixuan Zhao, Zhiteng Chao, Jing Ye, Wen Wang, Yuan Cao, Shuai Chen, Xiaowei Li, Huawei Li
2020	—	`conf`	Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System. ASAP Dawen Xu, Ziyang Zhu, Cheng Liu, Ying Wang, Huawei Li, Lei Zhang, Kwang-Ting Cheng
2020	—	`conf`	Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs. ACM Great Lakes Symposium on VLSI Qingli Guo, Jing Ye, Jiliang Zhang, Yu Hu, Xiaowei Li, Huawei Li
2020	Misc	`conf`	Sequence Triggered Hardware Trojan in Neural Network Accelerator. VTS Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu
2020	J	`jnl`	Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Zhang, Krishnendu Chakrabarty, Zebo Peng, Ahmed Rezine, Huawei Li, Petru Eles, Jianhui Jiang
2020	Misc	`conf`	Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. VTS Rajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Münch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui
2020	—	`conf`	Survey: Hardware Trojan Detection for Netlist. ATS Yipei Yang, Jing Ye, Yuan Cao, Jiliang Zhang, Xiaowei Li, Huawei Li, Yu Hu
2020	A*	`conf`	Towards State-Aware Computation in ReRAM Neural Networks. DAC Yintao He, Ying Wang, Xiandong Zhao, Huawei Li, Xiaowei Li
2019	—	`conf`	A Memristor-based Scan Hold Flip-Flop. NVMSA Aijiao Cui, Zhenxing Chang, Ziming Wang, Gang Qu, Huawei Li
2019	A*	`conf`	A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs. DAC Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li
2019	J	`jnl`	A QoS-QoR Aware CNN Accelerator Design Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Huawei Li, Long Cheng, Xiaowei Li
2019	Misc	`conf`	A Secure and Low-overhead Active IC Metering Scheme. VTS Aijiao Cui, Yan Yang, Gang Qu, Huawei Li
2019	A	`conf`	An Agile Precision-Tunable CNN Accelerator based on ReRAM. ICCAD Yintao He, Ying Wang, Yongchen Wang, Huawei Li, Xiaowei Li
2019	A	`conf`	China Test Conference (CTC) - Extending the Global Test Forum to China. ITC Huawei Li, Xiaowei Li, Yinhe Han
2019	J	`jnl`	Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yun Cheng, Huawei Li, Ying Wang, Xiaowei Li
2019	—	`conf`	Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval. USENIX ATC Shengwen Liang, Ying Wang, Youyou Lu, Zhe Yang, Huawei Li, Xiaowei Li
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	—	`conf`	Exploring emerging CNFET for efficient last level cache design. ASP-DAC Dawen Xu, Li Li, Ying Wang, Cheng Liu, Huawei Li
2019	C	`conf`	Fuzzy Association Rule Mining Algorithm Based on Load Classifier. ICDS Jing Chen, Hui Zheng, Peng Li, Zhenjiang Zhang, Huawei Li, Wei Liu
2019	—	`conf`	GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network. ATS Renjie Lu, Haihua Shen, Yu Su, Huawei Li, Xiaowei Li
2019	J	`jnl`	HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection. CoRR Renjie Lu, Haihua Shen, Feng Zhang, Huawei Li, Wei Zhao, Xiaowei Li
2019	—	`conf`	Implementation of Parametric Hardware Trojan in FPGA. ITC-Asia Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li, Yu Hu
2019	B	`conf`	InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. FPL Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li
2019	—	`conf`	Instruction Vulnerability Test and Code Optimization Against DVFS Attack. ITC-Asia JunYing Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang
2019	A	`conf`	Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. DATE Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li
2019	Misc	`conf`	Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems. VTS Wen Li, Ying Wang, Huawei Li, Xiaowei Li
2019	J	`jnl`	MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems. ACM J. Emerg. Technol. Comput. Syst. Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li
2019	—	`conf`	P ASP-DAC Wen Li, Ying Wang, Huawei Li, Xiaowei Li
2019	C	`conf`	RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime. ICCD Wen Li, Ying Wang, Huawei Li, Xiaowei Li
2019	—	`conf`	Resilient Neural Network Training for Accelerators with Computing Errors. ASAP Dawen Xu, KouZi Xing, Cheng Liu, Ying Wang, Yulin Dai, Long Cheng, Huawei Li, Lei Zhang
2019	J	`jnl`	Scan Chain Based Attacks and Countermeasures: A Survey. IEEE Access Xiaowei Li, Wenjie Li, Jing Ye, Huawei Li, Yu Hu
2019	—	`conf`	Squeezing the Last MHz for CNN Acceleration on FPGAs. ITC-Asia Li Li, Dawen Xu, KouZi Xing, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li
2019	A*	`conf`	Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis. DAC Yongchen Wang, Ying Wang, Huawei Li, Cong Shi, Xiaowei Li
2019	C	`conf`	iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. IOLTS Kuozhong Zhang, JunYing Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang
2018	J	`jnl`	A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Huawei Li, Xiaowei Li
2018	J	`jnl`	A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li
2018	—	`conf`	A New Scheme to Extract PUF Information by Scan Chain. ATS Aijiao Cui, Wei Zhou, Gang Qu, Huawei Li
2018	—	`conf`	A low-overhead PUF based on parallel scan design. ASP-DAC Wenxuan Wang, Aijiao Cui, Gang Qu, Huawei Li
2018	A	`conf`	A retrospective evaluation of energy-efficient object detection solutions on embedded devices. DATE Ying Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li, Xiaowei Li
2018	—	`conf`	Bias PUF based Secure Scan Chain Design. AsianHOST Wenjie Li, Jing Ye, Xiaowei Li, Huawei Li, Yu Hu
2018	J	`jnl`	CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency. J. Comput. Sci. Technol. Faqiang Sun, Guihai Yan, Xin He, Huawei Li, Yinhe Han
2018	A	`conf`	FCN-engine: accelerating deconvolutional layers in classic CNN processors. ICCAD Dawen Xu, Kaijie Tu, Ying Wang, Cheng Liu, Bingsheng He, Huawei Li
2018	—	`conf`	Hardware Trojan Detection Based on Signal Correlation. ATS Wei Zhao, Haihua Shen, Huawei Li, Xiaowei Li
2018	Misc	`conf`	Innovative practices on challenges, opportunities, and solutions to hardware security. VTS Sohrab Aftabjahani, Jason Oberg, Michael Chen, Huawei Li
2018	J	`jnl`	LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection. IEEE Trans. Very Large Scale Integr. Syst. Haihua Shen, Huazhe Tan, Huawei Li, Feng Zhang, Xiaowei Li
2018	—	`conf`	Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors. ITC-Asia Ying Wang, Wen Li, Huawei Li, Xiaowei Li
2018	A	`conf`	Lightweight Timing Channel Protection for Shared DRAM Controller. ITC Ying Wang, Wen Li, Huawei Li, Xiaowei Li
2018	Misc	`conf`	Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF. VTS Jing Ye, Qingli Guo, Yu Hu, Huawei Li, Xiaowei Li
2018	J	`jnl`	On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yun Cheng, Huawei Li, Ying Wang, Haihua Shen, Bo Liu, Xiaowei Li
2018	—	`conf`	Small Trojan Testing Using Bounded Model Checking. ITC-Asia Ying Zhang, Lu Yu, Huawei Li, Jianhui Jiang
2018	—	`conf`	XORiM: A case of in-memory bit-comparator implementation and its performance implications. ASP-DAC Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li
2017	—	`conf`	A New Active IC Metering Technique Based on Locking Scan Cells. ATS Aijiao Cui, Xuesen Qian, Gang Qu, Huawei Li
2017	—	`conf`	ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory. ASP-DAC Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	Misc	`conf`	Flip-flop clustering based trace signal selection for post-silicon debug. VTS Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li
2017	—	`conf`	How to Secure Scan Design Against Scan-Based Side-Channel Attacks? ATS Wei Zhou, Aijiao Cui, Huawei Li, Gang Qu
2017	Misc	`conf`	Innovative practices session 10C formal verification practices in industry. VTS Huawei Li, Xiaowei Li
2017	—	`conf`	On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios. ATS Huina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, Xiaowei Li
2017	A*	`conf`	Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR. DAC Ying Wang, Huawei Li, Xiaowei Li
2017	J	`jnl`	Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Jiachao Deng, Yuntan Fang, Huawei Li, Xiaowei Li
2017	J	`jnl`	Retention-Aware DRAM Assembly and Repair for Future FGR Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li
2017	J	`jnl`	STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li
2017	—	`conf`	Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems. Conf. Computing Frontiers Dawen Xu, Yi Liao, Ying Wang, Huawei Li, Xiaowei Li
2017	A	`conf`	Software-based online self-testing of network-on-chip using bounded model checking. ITC Ying Zhang, Krishnendu Chakrabarty, Huawei Li, Jianhui Jiang
2017	—	`conf`	Test and Reliability of Emerging Non-volatile Memories. ATS Said Hamdioui, Peyman Pouyan, Huawei Li, Ying Wang, Arijit Raychowdhury, Insik Yoon
2017	J	`jnl`	Why current secure scan designs fail and how to fix them? Integr. Aijiao Cui, Yanhui Luo, Huawei Li, Gang Qu
2016	J	`jnl`	A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands. ACM Trans. Design Autom. Electr. Syst. Song Jin, Songwei Pei, Yinhe Han, Huawei Li
2016	C	`conf`	A new countermeasure against scan-based side-channel attacks. ISCAS Yanhui Luo, Aijiao Cui, Gang Qu, Huawei Li
2016	J	`jnl`	Abstraction-Guided Simulation Using Markov Analysis for Functional Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, Sandip Kundu
2016	A	`conf`	An accurate algorithm for computing mutation coverage in model checking. ITC Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li, Bo Liu
2016	—	`conf`	An ultra-low overhead LUT-based PUF for FPGA. AsianHOST Jiadong Wang, Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li
2016	J	`jnl`	CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition. IEEE Trans. Computers Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li
2016	A*	`conf`	DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. DAC Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li
2016	A*	`conf`	DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. DAC Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li
2016	A	`conf`	Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage. DATE Ying Wang, Huawei Li, Xiaowei Li
2016	J	`jnl`	Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li
2016	J	`jnl`	LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs. Integr. Jun Zhou, Huawei Li, Tiancheng Wang, Xiaowei Li
2016	J	`jnl`	PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li
2016	Misc	`conf`	Path constraint solving based test generation for observability-enhanced branch coverage. VTS Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li
2016	—	`conf`	PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping. IGSC Faqiang Sun, Huawei Li, Yinhe Han, Guihai Yan, Jun Ma
2016	—	`conf`	Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools. ATS Yingxin Qiu, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li
2016	A	`conf`	Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices. ICCAD Ying Wang, Huawei Li, Xiaowei Li
2016	J	`jnl`	VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li
2015	—	`conf`	A Lightweight Timing Channel Protection for Shared Memory Controllers. ATS Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li
2015	—	`conf`	A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans. ISVLSI Yun Cheng, Ying Wang, Huawei Li, Xiaowei Li
2015	C	`conf`	A case of precision-tunable STT-RAM memory design for approximate neural network. ISCAS Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li
2015	J	`jnl`	An on-chip frequency programmable test clock generation and application method for small delay defect detection. Integr. Songwei Pei, Huawei Li, Song Jin, Jun Liu, Xiaowei Li
2015	J	`jnl`	Data Remapping for Static NUCA in Degradable Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
2015	J	`jnl`	Economizing TSV Resources in 3-D Network-on-Chip Design. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li
2015	—	`conf`	Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing. ASP-DAC Songwei Pei, Ye Geng, Huawei Li, Jun Liu, Song Jin
2015	—	`conf`	On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island. VLSI-DAT Song Jin, Songwei Pei, Yinhe Han, Huawei Li
2015	A*	`conf`	ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. DAC Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li
2015	A	`conf`	Retraining-based timing error mitigation for hardware neural networks. DATE Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu
2015	—	`conf`	TURO: A lightweight turn-guided routing scheme for 3D NoCs. COOL Chips Jun Zhou, Huawei Li, Tiancheng Wang, Ying Wang, Xiaowei Li
2015	—	`conf`	TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs. ATS Jun Zhou, Huawei Li, Tiancheng Wang, Sen Li, Ying Wang, Xiaowei Li
2015	A	`conf`	Temperature-aware software-based self-testing for delay faults. DATE Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita
2014	—	`conf`	A low power DRAM refresh control scheme for 3D memory cube. COOL Chips Ying Wang, Yinhe Han, Huawei Li
2014	—	`conf`	A novel abstraction-guided simulation approach using posterior probabilities for verification. VLSI-DAT Jian Wang, Huawei Li, Xiaowei Li
2014	—	`conf`	An On-Line Timing Error Detection Method for Silicon Debug. ATS Yun Cheng, Huawei Li, Xiaowei Li
2014	A	`conf`	Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. ICCAD Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li
2014	A	`conf`	Functional test generation guided by steady-state probabilities of abstract design. DATE Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li
2014	—	`conf`	HARS: A High-Performance Reliable Routing Scheme for 3D NoCs. ISVLSI Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li
2014	J	`jnl`	Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. Yuntan Fang, Huawei Li, Xiaowei Li
2014	J	`jnl`	Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach. ACM Trans. Archit. Code Optim. Shuangde Fang, Zidong Du, Yuntan Fang, Yuanjie Huang, Yang Chen, Lieven Eeckhout, Olivier Temam, Huawei Li, Yunji Chen, Chengyong Wu
2014	J	`jnl`	Reinventing Memory System Design for Many-Accelerator Architecture. J. Comput. Sci. Technol. Ying Wang, Lei Zhang, Yinhe Han, Huawei Li
2014	J	`jnl`	Test-Quality Optimization for Variable $n$ -Detections of Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. Dawen Xu, Huawei Li, Amirali Ghofrani, Kwang-Ting Cheng, Yinhe Han, Xiaowei Li
2014	J	`jnl`	ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels. IEEE Trans. Very Large Scale Integr. Syst. Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2013	J	`jnl`	Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. Ying Zhang, Huawei Li, Xiaowei Li
2013	C	`conf`	Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction. ISCAS Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li
2013	—	`conf`	Path Constraint Solving Based Test Generation for Hard-to-Reach States. Asian Test Symposium Yanhong Zhou, Tiancheng Wang, Tao Lv, Huawei Li, Xiaowei Li
2013	Misc	`conf`	RSAK: Random stream attack for phase change memory in video applications. VTS Yuntan Fang, Huawei Li, Xiaowei Li
2013	J	`jnl`	Test Path Selection for Capturing Delay Failures Under Statistical Timing Model. IEEE Trans. Very Large Scale Integr. Syst. Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2013	J	`jnl`	Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction. IEEE Trans. Very Large Scale Integr. Syst. Song Jin, Yinhe Han, Huawei Li, Xiaowei Li
2012	J	`jnl`	A High-Precision On-Chip Path Delay Measurement Architecture. IEEE Trans. Very Large Scale Integr. Syst. Songwei Pei, Huawei Li, Xiaowei Li
2012	J	`jnl`	Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume. IEEE Trans. Very Large Scale Integr. Syst. Songwei Pei, Huawei Li, Xiaowei Li
2012	—	`conf`	SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write. Asian Test Symposium Yuntan Fang, Huawei Li, Xiaowei Li
2012	—	`conf`	Statistical SDFC: A metric for evaluating test quality of small delay faults. VLSI-DAT Xuefeng Zhu, Huawei Li, Xiaowei Li
2012	J	`jnl`	Testable Path Selection and Grouping for Faster Than At-Speed Testing. IEEE Trans. Very Large Scale Integr. Syst. Xiang Fu, Huawei Li, Xiaowei Li
2011	—	`conf`	A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications. Asian Test Symposium Yuntan Fang, Huawei Li, Xiaowei Li
2011	J	`jnl`	A New Multiple-Round Dimension-Order Routing for Networks-on-Chip. IEICE Trans. Inf. Syst. Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2011	Misc	`conf`	A unified test architecture for on-line and off-line delay fault detections. VTS Songwei Pei, Huawei Li, Xiaowei Li
2011	A*	`conf`	An abacus turn model for time/space-efficient reconfigurable routing. ISCA Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li
2011	A	`conf`	Flex memory: Exploiting and managing abundant off-chip optical bandwidth. DATE Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
2011	J	`jnl`	Path Delay Test Generation Toward Activation of Worst Case Coupling Effects. IEEE Trans. Very Large Scale Integr. Syst. Minjin Zhang, Huawei Li, Xiaowei Li
2011	J	`jnl`	Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li
2011	J	`jnl`	Statistical lifetime reliability optimization considering joint effect of process variation and aging. Integr. Song Jin, Yinhe Han, Huawei Li, Xiaowei Li
2010	A	`conf`	Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. DATE Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2010	C	`conf`	Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. PRDC Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
2010	—	`conf`	An Efficient Algorithm for Finding a Universal Set of Testable Long Paths. Asian Test Symposium Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2010	A	`conf`	An on-chip clock generation scheme for faster-than-at-speed delay testing. DATE Songwei Pei, Huawei Li, Xiaowei Li
2010	Misc	`conf`	Fast path selection for testing of small delay defects considering path correlations. VTS Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2010	—	`conf`	Graph partition based path selection for testing of small delay defects. ASP-DAC Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2010	—	`conf`	On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing. Asian Test Symposium Xiang Fu, Huawei Li, Xiaowei Li
2010	A	`conf`	On generation of a universal path candidate set containing testable long paths. ITC Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2010	—	`conf`	P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework. Asian Test Symposium Song Jin, Yinhe Han, Huawei Li, Xiaowei Li
2010	—	`conf`	Software-Based Self-Testing of Processors Using Expanded Instructions. Asian Test Symposium Ying Zhang, Huawei Li, Xiaowei Li
2010	J	`jnl`	Testable Critical Path Selection Considering Process Variation. IEICE Trans. Inf. Syst. Xiang Fu, Huawei Li, Xiaowei Li
2010	A	`conf`	nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. ITC Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li
2009	—	`conf`	A Low Overhead On-Chip Path Delay Measurement Circuit. Asian Test Symposium Songwei Pei, Huawei Li, Xiaowei Li
2009	C	`conf`	A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. PRDC Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2009	—	`conf`	A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. Asian Test Symposium Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu
2009	Misc	`conf`	Automatic Selection of Internal Observation Signals for Design Verification. VTS Tao Lv, Huawei Li, Xiaowei Li
2009	C	`conf`	Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. PRDC Songwei Pei, Huawei Li, Xiaowei Li
2009	C	`conf`	Impact of Hazards on Pattern Selection for Small Delay Defects. PRDC Jie Wang, Huawei Li, Yinghua Min, Xiaowei Li, Huaguo Liang
2009	—	`conf`	M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. Asian Test Symposium Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan
2009	J	`jnl`	On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. IEEE Trans. Very Large Scale Integr. Syst. Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li
2009	J	`jnl`	Selected Crosstalk Avoidance Code for Reliable Network-on-Chip. J. Comput. Sci. Technol. Ying Zhang, Huawei Li, Xiaowei Li
2009	C	`conf`	Small Delay Fault Simulation for Sequential Circuits. PRDC Li Liu, Jishun Kuang, Huawei Li
2008	—	`conf`	A Case Study on At-Speed Testing for a Gigahertz Microprocessor. DELTA Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li
2008	—	`conf`	A Scan-Based Delay Test Method for Reduction of Overtesting. DELTA Hui Liu, Huawei Li, Yu Hu, Xiaowei Li
2008	—	`conf`	A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. ASP-DAC Fei Wang, Yu Hu, Huawei Li, Xiaowei Li
2008	Misc	`conf`	Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. VTS Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu
2008	J	`jnl`	Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. J. Comput. Sci. Technol. Da Wang, Yu Hu, Huawei Li, Xiaowei Li
2008	A	`conf`	Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. ITC Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang
2008	Misc	`conf`	Multiple Coupling Effects Oriented Path Delay Test Generation. VTS Minjin Zhang, Huawei Li, Xiaowei Li
2008	—	`conf`	Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance. ATS Ying Zhang, Huawei Li, Xiaowei Li
2008	—	`conf`	Robust test generation for power supply noise induced path delay faults. ASP-DAC Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li
2008	—	`conf`	Static Crosstalk Noise Analysis with Transition Map. DELTA Minjin Zhang, Huawei Li, Xiaowei Li
2007	—	`conf`	A Routing Algorithm for Random Error Tolerance in Network-on-Chip. HCI (4) Lei Zhang, Huawei Li, Xiaowei Li
2007	—	`conf`	Bug analysis and corresponding error models in real designs. HLDVT Tao Lv, Tong Xu, Yang Zhao, Huawei Li, Xiaowei Li
2007	J	`jnl`	Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. IEEE Trans. Very Large Scale Integr. Syst. Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra
2007	A	`conf`	The design-for-testability features of a general purpose microprocessor. ITC Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Rui Li, Huawei Li, Yu Hu, Xiaowei Li
2006	—	`conf`	An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains. ATS Tao Lv, Ling-Yi Liu, Yang Zhao, Huawei Li, Xiaowei Li
2006	J	`jnl`	Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Trans. Inf. Syst. Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen
2006	J	`jnl`	Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. IEEE Trans. Instrum. Meas. Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra
2006	B	`conf`	Fast Packet Classification using Group Bit Vector. GLOBECOM Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han
2006	J	`jnl`	Response compaction for system-on-a-chip based on advanced convolutional codes. Sci. China Ser. F Inf. Sci. Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra
2006	Misc	`conf`	Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. VTS Huawei Li, Pei-Fu Shen, Xiaowei Li
2006	—	`conf`	Test data compression based on clustered random access scan. ATS Yu Hu, Cheng Li, Jia Li, Yinhe Han, Xiaowei Li, Wei Wang, Huawei Li, Laung-Terng Wang, Xiaoqing Wen
2005	J	`jnl`	An innovative free memory design for network processors in home network gateway. IEEE Trans. Consumer Electron. Shuguang Gong, Huawei Li, Xiaowei Li
2005	C	`conf`	Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. PRDC Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen
2005	—	`conf`	Design of an efficient memory subsystem for network processor. ASP-DAC Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li
2005	—	`conf`	Non-robust Test Generation for Crosstalk-Induced Delay Faults. Asian Test Symposium Pei-Fu Shen, Huawei Li, Yong-Jun Xu, Xiaowei Li
2005	J	`jnl`	Selection of Crosstalk-Induced Faults in Enhanced Delay Test. J. Electron. Test. Huawei Li, Xiaowei Li
2005	J	`jnl`	Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. J. Comput. Sci. Technol. Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra
2005	—	`conf`	Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. ASP-DAC Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
2005	—	`conf`	Using MUXs Network to Hide Bunches of Scan Chains. ISQED Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
2005	J	`jnl`	Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Trans. Inf. Syst. Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen
2004	—	`conf`	Pair Balance-Based Test Scheduling for SOCs. Asian Test Symposium Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li
2004	—	`conf`	Rapid and Energy-Efficient Testing for Embedded Cores. Asian Test Symposium Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
2004	—	`conf`	Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. DFT Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
2003	J	`jnl`	A Novel RT-Level Behavioral Description Based ATPG Method. J. Comput. Sci. Technol. Zhigang Yin, Yinghua Min, Xiaowei Li, Huawei Li
2003	—	`conf`	Delay Test Pattern Generation Considering Crosstalk-Induced Effects. Asian Test Symposium Huawei Li, Yue Zhang, Xiaowei Li
2003	—	`conf`	Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. Asian Test Symposium Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra
2002	J	`jnl`	Clustering of behavioral phases in FSMs and its applications to VLSI test. Sci. China Ser. F Inf. Sci. Huawei Li, Yinghua Min, Zhongcheng Li
2002	—	`conf`	Test Power Optimization Techniques for CMOS Circuits. Asian Test Symposium Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min
2001	—	`conf`	An RT-Level ATPG Based on Clustering of Circuit States. Asian Test Symposium Huawei Li, Yinghua Min, Zhongcheng Li
2001	—	`conf`	Reducing Power Dissipation during At-Speed Test Application. DFT Xiaowei Li, Huawei Li, Yinghua Min
2000	J	`jnl`	Reduction of Number of Paths to be Tested in Delay Testing. J. Electron. Test. Huawei Li, Zhongcheng Li, Yinghua Min
1998	—	`conf`	Delay Testing with Double Observations. Asian Test Symposium Huawei Li, Zhongcheng Li, Yinghua Min