Hua Xiang

40 papers A* 4A 13Journal 10Unranked 12
YearRankTypeTitle / Venue / Authors
2025 J jnl
MaskOpt: A Large-Scale Mask Optimization Dataset to Advance AI in Integrated Circuit Manufacturing.
CoRR
Yuting Hu, Lei Zhuang, Hua Xiang, Jinjun Xiong, Gi-Joon Nam
2023 — conf
Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops.
ISVLSI
Chunkai Fu, Ben Trombley, Hua Xiang, Gi-Joon Nam, Jiang Hu
2022 A conf
A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions.
ICCAD
Rongjian Liang, Hua Xiang, Jinwook Jung, Jiang Hu, Gi-Joon Nam
2022 J jnl
Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi N. Reddy, Shyam Ramji, Gi-Joon Nam, Jiang Hu
2021 A conf
FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer.
ICCAD
Rongjian Liang, Jinwook Jung, Hua Xiang, Lakshmi N. Reddy, Alexey Lvov, Jiang Hu, Gi-Joon Nam
2020 — conf
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network.
ISPD
Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi N. Reddy, Shyam Ramji, Gi-Joon Nam, Jiang Hu
2020 A conf
Routing-Free Crosstalk Prediction.
ICCAD
Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, Gi-Joon Nam
2020 A conf
Self-Aligned Double-Patterning Aware Legalization.
DATE
Hua Xiang, Gi-Joon Nam, Gustavo E. Téllez, Shyam Ramji, Xiaoqing Xu
2016 — conf
Gate movement for timing improvement on row based Dual-VDD designs.
ISQED
Hua Xiang, Lakshmi N. Reddy, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu
2014 A* conf
Row Based Dual-VDD Island Generation and Placement.
DAC
Hua Xiang, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu
2013 A conf
Depth controlled symmetric function fanin tree restructure.
ICCAD
Hua Xiang, Lakshmi N. Reddy, Louise Trevillyan, Ruchir Puri
2013 A conf
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.
ICCAD
Minsik Cho, Hua Xiang, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri
2013 — conf
Network flow based datapath bit slicing.
ISPD
Hua Xiang, Minsik Cho, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri
2010 A* conf
History-based VLSI legalization using network flow.
DAC
Minsik Cho, Haoxing Ren, Hua Xiang, Ruchir Puri
2010 — conf
Logical and physical restructuring of fan-in trees.
ISPD
Hua Xiang, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho
2008 J jnl
Fast Dummy-Fill Density Analysis With Coupling Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
2008 J jnl
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
2008 J jnl
Track Routing and Optimization for Yield.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
2007 — conf
Coupling-aware Dummy Metal Insertion for Lithography.
ASP-DAC
Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang
2007 — conf
Dummy fill density analysis with coupling constraints.
ISPD
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
2007 — conf
Is your layout density verification exact?: a fast exact algorithm for density calculation.
ISPD
Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
2007 — conf
OPC-Friendly Bus Driven Floorplanning.
ISQED
Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong
2007 A* conf
TROY: Track Router with Yield-driven Wire Planning.
DAC
Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
2006 J jnl
An ECO routing algorithm for eliminating coupling-capacitance violations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
2006 A conf
Wire density driven global routing for CMP variation and timing.
ICCAD
Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
2005 J jnl
An algorithm for integrated pin assignment and buffer planning.
ACM Trans. Design Autom. Electr. Syst.
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
2005 — conf
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.
ISQED
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
2005 — conf
Wire Planning with Bounded Over-the-Block Wires.
ISQED
Hua Xiang, I-Min Liu, Martin D. F. Wong
2004 J jnl
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
2004 — conf
An ECO algorithm for eliminating crosstalk violations.
ISPD
Hua Xiang, Kai-Yuan Chao, D. F. Wong
2004 J jnl
Bus-driven floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
2004 — —
New Strategies for High Performance VLSI Physical Design
Hua Xiang
2003 A conf
Bus-Driven Floorplanning.
ICCAD
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
2003 J jnl
Min-cost flow-based algorithm for simultaneous pin assignment and routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
2003 A conf
Wire type assignment for FPGA routing.
FPGA
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
2002 A conf
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem.
DATE
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
2002 A* conf
An algorithm for integrated pin assignment and buffer planning.
DAC
Hua Xiang, D. F. Wong, Xiaoping Tang
2002 A conf
ECO algorithms for removing overlaps between power rails and signal wires.
ICCAD
Hua Xiang, Kai-Yuan Chao, D. F. Wong
2001 A conf
A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints.
ICCAD
Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong
2001 A conf
An Algorithm for Simultaneous Pin Assignment and Routing.
ICCAD
Hua Xiang, Xiaoping Tang, D. F. Wong