Hua-Yu Chang

20 papers A* 5A 3C 1Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2026 — conf
Any-Angle Die-to-Die Routing for Advanced Packages with Asymmetric Pin Row Structures, Via Constraints, and Shielding-Aware Reservation.
ISPD
Hsin-Tzu Chang, Iris Hui-Ru Jiang, Hua-Yu Chang, Chun-Hao Lai
2024 A conf
Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules.
ICCAD
Yu-Yang Chen, Yi-Chen Lin, Tzu-Han Hsu, Iris Hui-Ru Jiang, Tung-Chieh Chen, Tai-Chen Chen, Hua-Yu Chang
2022 — conf
Challenges for Automating Package Routing.
ISPD
Wen-Hao Liu, Bing Chen, Hua-Yu Chang, Gary Lin, Zi-Shen Lin
2019 — conf
Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement.
ISPD
Hua-Yu Chang, Iris Hui-Ru Jiang
2018 — conf
Recent Research and Challenges in Multiple Patterning Layout Decomposition.
ISVLSI
Iris Hui-Ru Jiang, Hua-Yu Chang
2017 J jnl
Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Iris Hui-Ru Jiang, Hua-Yu Chang
2016 A* conf
Multiple patterning layout decomposition considering complex coloring rules.
DAC
Hua-Yu Chang, Iris Hui-Ru Jiang
2015 J jnl
Feature detection for image analytics via FPGA acceleration.
IBM J. Res. Dev.
Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir A. Jamsek, Gi-Joon Nam
2014 A* conf
Functional ECO Using Metal-Configurable Gate-Array Spare Cells.
DAC
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2014 A conf
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations.
ICCAD
Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes
2013 J jnl
ECO Optimization Using Metal-Configurable Gate-Array Spare Cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2012 J jnl
ECOS: Stable Matching Based Metal-Only ECO Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Iris Hui-Ru Jiang, Hua-Yu Chang
2012 J jnl
Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2012 A* conf
Timing ECO optimization using metal-configurable gate-array spare cells.
DAC
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2012 J jnl
WiT: Optimal Wiring Topology for Electromigration Avoidance.
IEEE Trans. Very Large Scale Integr. Syst.
Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang
2011 A* conf
Simultaneous functional and timing ECO.
DAC
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2011 A conf
Timing ECO optimization via Bézier curve smoothing and fixability identification.
ICCAD
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2010 C conf
Live Demo: ECOS 1.0: A metal-only ECO synthesizer.
ISCAS
Iris Hui-Ru Jiang, Hua-Yu Chang
2010 — conf
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles.
ISPD
Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang
2009 A* conf
Matching-based minimum-cost spare cell selection for design changes.
DAC
Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung