Hu He

36 papers A* 2A 1C 2Journal 22Unranked 9
YearRankTypeTitle / Venue / Authors
2026 J jnl
Data-Driven Sensitivity Analysis and Hybrid Multi-Objective Optimization for Ultra-High Performance Klystron.
IEEE Access
Hezhang Zhao, Limin Sun, Shifeng Li, Hu He, Hua Huang, Zhenbang Liu, Wenhao Wang, Ke He, Dongwenlong Wu, Hongge Ma
2025 A* conf
RICH Prefetcher: Storing Rich Information in Memory to Trade Capacity and Bandwidth for Latency Hiding.
MICRO
Ningzhi Ai, Wenjian He, Hu He, Jing Xia, Heng Liao, Guowei Zhang
2025 J jnl
RISC-V-Based GPGPU With Vector Capabilities for High-Performance Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Jingzhou Li, Fangfei Yu, Mingyuan Ma, Wei Liu, Yuhan Wang, Hualin Wu, Hu He
2024 — conf
HCRF: A Hardware Checkpoint-based Recovery Framework in light dual-core lockstep processors.
ACM Great Lakes Symposium on VLSI
Jingzhou Li, Huaiyu Chen, Wenbin Zhang, Hu He
2024 C conf
Ventus: A High-performance Open-source GPGPU Based on RISC-V and Its Vector Extension.
ICCD
Jingzhou Li, Kexiang Yang, Chufeng Jin, Xudong Liu, Zexia Yang, Fangfei Yu, Yujie Shi, Mingyuan Ma, Li Kong, Jing Zhou, Hualin Wu, Hu He
2023 J jnl
A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit.
IEEE Trans. Circuits Syst. II Express Briefs
Hanwen Gong, Hu He, Bin Gao, Jianshi Tang, Jian Yu, Dabin Wu, Junren Chen, Qingtian Zhang, Xing Mou, He Qian, Huaqiang Wu
2023 — conf
ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing.
ICTA
Hanwen Gong, Hu He, Bin Gao, Jianshi Tang, Qingtian Zhang, He Qian, Huaqiang Wu
2023 J jnl
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hanwen Gong, Hu He, Liyang Pan, Bin Gao, Jianshi Tang, Sining Pan, Jianing Li, Peng Yao, Dabin Wu, He Qian, Huaqiang Wu
2023 J jnl
CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system.
Sci. China Inf. Sci.
Ruihua Yu, Wenqiang Zhang, Bin Gao, Yiwen Geng, Peng Yao, Yuyi Liu, Qingtian Zhang, Jianshi Tang, Dong Wu, Hu He, Ning Deng, He Qian, Huaqiang Wu
2021 J jnl
A memory neural system built based on spiking neural network.
Neurocomputing
Hu He, Qilin Wang, Xu Yang, Yunlin Lei, Jia Cai, Ning Deng
2021 — conf
HARNS: High-level Architectural Model of RRAM based Computing-in-memory NPU.
ICTA
Yanhai Jiang, Bin Gao, Jianshi Tang, Dabin Wu, Hu He, He Qian, Huaqiang Wu
2020 — conf
The Algorithm of Spiking Neural Network And Application in Poker Games.
ICMSSP
Liya Dong, Qilin Wang, Hu He
2019 J jnl
A Processing-in-Memory Architecture Programming Paradigm for Wireless Internet-of-Things Applications.
Sensors
Xu Yang, Yumin Hou, Hu He
2019 J jnl
CDSP: A Solution for Privacy and Security of Multimedia Information Processing in Industrial Big Data and Internet of Things.
Sensors
Xu Yang, Yumin Hou, Junping Ma, Hu He
2019 A* conf
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.
DAC
Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian
2019 J jnl
Exploration of a mechanism to form bionic, self-growing and self-organizing neural network.
Artif. Intell. Rev.
Xu Yang, Guo Liu, Songgaojun Deng, Zichao Wei, Hu He, Yingjie Shang, Ning Deng
2019 J jnl
Improving ILP via Fused In-Order Superscalar and VLIW Instruction Dispatch Methods.
J. Circuits Syst. Comput.
Yumin Hou, Xu Wang, Jiawei Fu, Junping Ma, Hu He, Xu Yang
2019 J jnl
On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yumin Hou, Hu He, Kaveh Shamsi, Yier Jin, Dong Wu, Huaqiang Wu
2018 — conf
R2D2: Runtime reassurance and detection of A2 Trojan.
HOST
Yumin Hou, Hu He, Kaveh Shamsi, Yier Jin, Dong Wu, Huaqiang Wu
2017 J jnl
On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage.
Comput. J.
Hu He, Xu Yang, Yanjun Zhang
2016 J jnl
FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW.
VLSI Design
Yumin Hou, Hu He, Xu Yang, Deyuan Guo, Xu Wang, Jiawei Fu, Keni Qiu
2014 J jnl
A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA.
IEEE Trans. Very Large Scale Integr. Syst.
Jianfeng Zhu, Liyang Pan, Yaru Yan, Dong Wu, Hu He
2014 J jnl
An Implementation of Message-Passing Interface over VxWorks for Real-Time Embedded Multi-Core Systems.
Comput. J.
Xu Yang, Deyuan Guo, Hu He, Haijing Tang, Yanjun Zhang
2013 J jnl
Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems.
IET Wirel. Sens. Syst.
Xu Yang, Yanjun Zhang, Dake Liu, Deyuan Guo, Hu He
2012 J jnl
An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems.
Sensors
Xu Yang, Hu He
2011 A conf
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).
FPGA
Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan
2011 J jnl
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect.
J. Electron. Test.
Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan
2011 J jnl
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect.
J. Electron. Test.
Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan
2009 J jnl
A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures.
J. Low Power Electron.
Yang Xu, Hu He, Yihe Sun
2009 C conf
Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism.
DSD
Zheng Shen, Hu He, Yihe Sun
2008 — conf
Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC.
DELTA
Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei
2007 — conf
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture.
ASAP
Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng
2007 J jnl
A Video Specific Instruction Set Architecture for ASIP design.
VLSI Design
Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun
2007 J jnl
Heuristic on a Novel Power Management System Cooperating with Compiler.
J. Low Power Electron.
Yang Xu, Hu He, Zhou Zhixiong, Yanjun Zhang, Yihe Sun
2006 — conf
VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design.
IIH-MSP
Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun
2005 — conf
A new register file access architecture for software pipelining in VLIW processors.
ASP-DAC
Yanjun Zhang, Hu He, Yihe Sun