Hsing-Chung Liang

14 papers A 2B 2Misc 1Journal 6Unranked 3
YearRankTypeTitle / Venue / Authors
2021 B conf
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering.
ETS
Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
2021 B conf
GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer.
ETS
Hua-Ren Li, Hsing-Chung Liang
2021 A conf
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling.
ITC
Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
2020 A conf
Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis.
DATE
Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen
2009 J jnl
Improved Representatives for Judging Unrepairability and Deciding Economic Repair Solutions of Memories.
J. Circuits Syst. Comput.
Hsing-Chung Liang
2008 J jnl
Testing Transition Delay Faults in Modified Booth Multipliers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hsing-Chung Liang, Pao-Hsin Huang, Yan-Fei Tang
2006 — conf
Improved Representatives for Unrepairability Judging and Economic Repair Solutions of Memories.
MTDT
Hsing-Chung Liang, Le-Quen Tzeng
2005 J jnl
Identify unrepairability to speed-up spare allocation for repairing memories.
IEEE Trans. Reliab.
Hsing-Chung Liang, Wen-Chin Ho, Ming-Chieh Cheng
2000 J jnl
Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
J. Inf. Sci. Eng.
Hsing-Chung Liang, Chung-Len Lee
1999 — conf
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
Asian Test Symposium
Hsing-Chung Liang, Chung-Len Lee
1998 Misc conf
Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation.
VTS
Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1997 J jnl
Identifying invalid states for sequential circuit test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1996 — conf
Invalid State Identification for Sequential Circuit Test Generation.
Asian Test Symposium
Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1995 J jnl
Identifying Untestable Faults in Sequential Circuits.
IEEE Des. Test Comput.
Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen