Hsin-Wen Ting

22 papers Journal 17Unranked 5
YearRankTypeTitle / Venue / Authors
2018 J jnl
A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs.
IEEE Des. Test
Yen-Long Lee, Yu-Po Cheng, Soon-Jyh Chang, Hsin-Wen Ting
2018 J jnl
A VLSI On-Chip Analog High-Order Low-Pass Filter Performance Evaluation Strategy.
IEEE Trans. Instrum. Meas.
Hsin-Wen Ting, Chi-Yuan Chen
2017 J jnl
Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing.
IEEE Trans. Very Large Scale Integr. Syst.
I-Jen Chao, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting
2017 — conf
Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology.
ISOCC
Chi-Hsien Wu, Jau-Ji Jou, Hsin-Wen Ting, Shao-I Chu, Bing-Hong Liu
2016 J jnl
A Digital Testing Strategy for Characterizing an Analog Circuit Block.
IEEE Trans. Instrum. Meas.
Hsin-Wen Ting
2016 J jnl
Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs.
IEEE Trans. Instrum. Meas.
Chun-Po Huang, Hsin-Wen Ting, Soon-Jyh Chang
2015 J jnl
A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS.
Int. J. Circuit Theory Appl.
An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, Soon-Jyh Chang
2014 J jnl
A Low-Cost Stimulus Design for Linearity Test in SAR ADCs.
IEICE Trans. Electron.
An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, Soon-Jyh Chang
2012 J jnl
A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing.
IEICE Trans. Electron.
I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting
2012 J jnl
Digital-Compatible Testing Scheme for Operational Amplifier.
J. Electron. Test.
Hsin-Wen Ting
2012 J jnl
Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers.
IET Circuits Devices Syst.
Ren-Li Chen, Hsin-Wen Ting, Soon-Jyh Chang
2011 J jnl
A Design of Linearity Built-in Self-Test for Current-Steering DAC.
J. Electron. Test.
Hsin-Wen Ting, Soon-Jyh Chang, Su-Ling Huang
2011 — conf
A SAR ADC BIST for simplified linearity test.
SoCC
An-Sheng Chao, Soon-Jyh Chang, Hsin-Wen Ting
2011 J jnl
An Output Response Analyzer Circuit for ADC Built-in Self-Test.
J. Electron. Test.
Hsin-Wen Ting
2011 J jnl
Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs.
J. Electron. Test.
Jin-Fu Lin, Hsin-Wen Ting
2011 J jnl
Realization of High Octave Decomposition for Breast Cancer Feature Extraction on Ultrasound Images.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsieh-Wei Lee, King-Chu Hung, Bin-Da Liu, Sheau-Fang Lei, Hsin-Wen Ting
2011 J jnl
Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting, Chih-Hao Huang
2008 J jnl
A Histogram-Based Testing Method for Estimating A/D Converter Performance.
IEEE Trans. Instrum. Meas.
Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang
2007 J jnl
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST.
J. Electron. Test.
Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang
2006 — conf
A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design.
APCCAS
Ruei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu
2006 — conf
Histogram Based Testing Strategy for ADC.
ATS
Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang
2004 — conf
A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters.
Asian Test Symposium
Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang