Hsin-Shu Chen

33 papers C 9Journal 12Unranked 11
YearRankTypeTitle / Venue / Authors
2025 C conf
A 94.8% Peak-Efficiency 3-Level Buck Converter with Fast Flying Capacitor Charging Technique.
ISCAS
Chi-Wei Chen, Jia-Yi Chen, Hsin-Shu Chen
2025 C conf
An SRAM-Based PUF with High Native-Stability Using Alternative Configuration Technique.
ICCE
Sharon Isabelle Timotius, Yi-Lun Wang, Hsin-Shu Chen
2024 J jnl
Pulsed-Laser-Induced Single-Event Upset in Dynamic Comparator by Incorporating Experimental Parameters Into Simulations.
IEEE Trans. Instrum. Meas.
Shih-Bo Yu, Chun-Hao Liang, Chien-Ping Hung, Yu-Lin Chen, Pei-Kai Liao, Jia-Han Li, Hsin-Shu Chen, Chia-Ray Chen, Chien-Kai Tseng
2023 — conf
A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback.
MWSCAS
Jun-Yi Wu, Hsin-Shu Chen
2022 C conf
A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC.
ISCAS
Chi-Wei Chen, Chien-Yu Su, Hsin-Shu Chen
2021 C conf
Reconfigurable Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Frequency Scaling Techniques.
ISCAS
Tun-Yen Liao, Hsin-Shu Chen, Wen-Jong Wu
2020 C conf
A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration.
ISCAS
Hsin-Shu Chen, Sheng-Hsiang Huang, Hung-Yen Tai, Sen-Wei Lin, Shih-Wei Wu
2019 J jnl
A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System.
IEEE J. Solid State Circuits
Yao-Sheng Hu, Li-Yu Huang, Hsin-Shu Chen
2019 — conf
A Fast-Transient Switched-Capacitor DC-DC Converter with a Current Sensing Control Technique.
MWSCAS
Chi-Wei Chen, Hsin-Shu Chen, Wen-Jong Wu
2018 C conf
A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting.
ISCAS
Kai-Ren Cheng, Hsin-Shu Chen, Mickaël Lallart, Wen-Jong Wu
2018 — conf
A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System.
A-SSCC
Yao-Sheng Hu, Li-Yu Huang, Hsin-Shu Chen
2018 — conf
An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration.
A-SSCC
Yao-Sheng Hu, Jhao-Huei Lin, Ding-Guo Lin, Kai-Yue Lin, Hsin-Shu Chen
2017 C conf
A current average control method for transient-glitch reduction in variable frequency DC-DC converters.
ISCAS
Hsin-Shu Chen, Jia-Nan Tai, Yi-Jan Emery Chen, Jau-Horng Chen
2016 — conf
A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC.
A-SSCC
Yao-Sheng Hu, Po-Chao Huang, Mi-Ti Yang, Shih-Wei Wu, Hsin-Shu Chen
2016 — conf
A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique.
A-SSCC
Yao-Sheng Hu, Kai-Yue Lin, Hsin-Shu Chen
2016 J jnl
A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs
Yao-Sheng Hu, Po-Chao Huang, Hung-Yen Tai, Hsin-Shu Chen
2016 J jnl
An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tsung-Han Tsai, Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, Hsin-Shu Chen
2016 C conf
An 8-bit 900MS/S two-step SAR ADC.
ISCAS
Po-Chao Huang, Yao-Sheng Hu, Hung-Yen Tai, Hsin-Shu Chen
2014 — conf
11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS.
ISSCC
Hung-Yen Tai, Yao-Sheng Hu, Hung-Wei Chen, Hsin-Shu Chen
2014 — conf
A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS.
A-SSCC
Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen
2014 J jnl
A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chien-Jian Tseng, Chieh-Fan Lai, Hsin-Shu Chen
2014 J jnl
A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Hung-Yen Tai, Cheng-Hsueh Tsai, Pao-Yang Tsai, Hung-Wei Chen, Hsin-Shu Chen
2013 J jnl
A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chien-Jian Tseng, Yi-Chun Hsieh, Ching-Hua Yang, Hsin-Shu Chen
2012 J jnl
A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC.
IEEE J. Solid State Circuits
Chien-Jian Tseng, Hung-Wei Chen, Wei-Ting Shen, Wei-Chih Cheng, Hsin-Shu Chen
2012 — conf
A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS.
VLSIC
Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen
2012 J jnl
A High-Efficiency CMOS DC-DC Converter With 9-µs Transient Recovery Time.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pang-Jung Liu, Wei-Shan Ye, Jia-Nan Tai, Hsin-Shu Chen, Jau-Horng Chen, Yi-Jan Emery Chen
2012 — conf
A highly integrated class-D amplifier using driver delay hysteresis control.
VLSI-DAT
Jia-Nan Tai, Hsin-Shu Chen, Hang-Quei Chiu
2010 J jnl
A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop.
IEICE Trans. Electron.
Hsin-Shu Chen, Jyun-Cheng Lin
2009 J jnl
A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-µm CMOS.
IEEE J. Solid State Circuits
Hung-Wei Chen, I-Ching Chen, Huan-Chieh Tseng, Hsin-Shu Chen
2006 C conf
A 1.5-V 10-ppm/°C 2nd-order curvature-compensated CMOS bandgap reference with trimming.
ISCAS
Sen-Wen Hsiao, Yen-Chih Huang, David Liang, Hung-Wei Kevin Chen, Hsin-Shu Chen
2001 J jnl
A 14-b 20-Msamples/s CMOS pipelined ADC.
IEEE J. Solid State Circuits
Hsin-Shu Chen, Bang-Sup Song, Kantilal Bacrania
2001 — —
High-Resolution Nyquist -Rate Analog -to -Digital Converter
Hsin-Shu Chen
1999 — conf
Characterization of 1/f noise vs. number of gate stripes in MOS transistors.
ISCAS (2)
Hsin-Shu Chen, A. Ito