Hsie-Chia Chang

103 papers A 2B 1C 14Misc 2Journal 43Unranked 41
YearRankTypeTitle / Venue / Authors
2024 J jnl
GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation.
IEEE Open J. Circuits Syst.
Yu-Lun Hsu, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
2023 — conf
A MATE-GDBF Algorithm for Irregular Punctured LDPC Codes and Its Decoder Implementation.
APCCAS
Xiao-Juan Huang, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang, Sau-Gee Chen
2022 J jnl
A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories.
IEEE Open J. Circuits Syst.
Li-Wei Liu, Mu-Hua Yuan, Yen-Chin Liao, Hsie-Chia Chang
2022 Misc conf
A Clustering-based ML Scheme for Capacity Approaching Soft Level Sensing in 3D TLC NAND.
ICASSP
Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
2022 — conf
An Attention-based Neural Network on Multiple Speaker Diarization.
AICAS
Shao Wen Cheng, Kai Jyun Hung, Hsie-Chia Chang, Yen-Chin Liao
2022 J jnl
UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash Applications.
IEEE Open J. Circuits Syst.
Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
2021 C conf
A 33.2 Gbps/Iter. Reconfigurable LDPC Decoder Fully Compliant with 5G NR Applications.
ISCAS
Chieh-Yu Lin, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
2021 — conf
A 45.4x∼221.2x latency Improvement of SRP-5 Cryptographic Engine for Smart Grid Network.
A-SSCC
Ya-Yun Hou, Shaopeng Lai, Hung-Kun Chang, Yun-Wen Lu, Hsie-Chia Chang
2021 — conf
A Two-Stage Path Planning Engine for Robot Navigation System.
SoCC
Yu-En Hsu, Yen-Chin Liao, Hsie-Chia Chang
2021 — conf
F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors.
ISSCC
Sukhwan Lim, Yongpan Liu, Luca Benini, Tanay Karnik, Hsie-Chia Chang
2020 C conf
An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications.
ISCAS
Wei Chiang, Hsie-Chia Chang, Chen-Yi Lee
2020 A conf
Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification.
DATE
Yi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang
2020 J jnl
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits
Tony Chan Carusone, Mingoo Seok, Hsie-Chia Chang, Meng-Fan Chang
2019 J jnl
A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yen-Chin Liao, Chien Lin, Hsie-Chia Chang, Shu Lin
2019 — conf
A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR.
VLSI-DAT
Yun-Wen Lu, Antoon Purnal, Simon Vandenhende, Chen-Yi Lee, Ingrid Verbauwhede, Hsie-Chia Chang
2019 — conf
ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation.
SoCC
Wei-Chien Kuo, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
2018 — conf
A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS.
VLSI-DAT
Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong, Chen-Yi Lee
2018 C conf
A 188-Length Full Code Rate 333Mbps 1.08mm
ISCAS
Po-Hsun Chang, Chen-Yang Lin, Chia-Hsiang Sun, Yen-Chin Liao, Hsie-Chia Chang
2018 B conf
Generalized Globally-Coupled Low-Density Parity-Check Codes.
ITW
Yen-Chin Liao, Hsie-Chia Chang, Shu Lin
2018 — conf
Scalable Globally-Coupled Low-Density Parity Check Codes.
ISTC
Yen-Chin Liao, Hsie-Chia Chang, Shu Lin
2017 J jnl
An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Szu-Chi Chung, Chun-Yuan Yu, Sung-Shine Lee, Hsie-Chia Chang, Chen-Yi Lee
2017 J jnl
Re-Polarization Processing in Extended Polar Codes.
IEICE Trans. Commun.
Yu-Ming Huang, Hsie-Chia Chang, Hsiang-Pang Li
2016 J jnl
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang
2016 — conf
A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications.
A-SSCC
Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2016 J jnl
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs
Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 — conf
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications.
ESSCIRC
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 C conf
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications.
ISCAS
Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 — conf
A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process.
A-SSCC
Kelvin Yi-Tse Lai, Ming-Feng Shiu, Yi-Wen Lu, Yingchieh Ho, Yu-Chi Kao, Yu-Tao Yang, Gary Wang, Keng-Ming Liu, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder.
IEEE Trans. Circuits Syst. II Express Briefs
Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
2015 J jnl
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability.
IEEE Trans. Very Large Scale Integr. Syst.
Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
2015 — conf
Design of LT code degree distribution with profiled output ripple size.
SiPS
Kuo-Kuang Yen, Yen-Chin Liao, Hsie-Chia Chang
2015 J jnl
Efficient Hardware Architecture of η
IEEE Trans. Very Large Scale Integr. Syst.
Szu-Chi Chung, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee
2015 J jnl
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2014 — conf
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network.
A-SSCC
Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee
2014 J jnl
A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi-Min Lin, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee
2014 — conf
A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring.
A-SSCC
Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, Ming-Feng Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee
2014 — conf
A 7.11mJ/Gb/query data-driven machine learning processor (D
VLSIC
Chang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee
2014 C conf
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes.
ISCAS
Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2014 J jnl
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee
2014 J jnl
Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes.
IEEE Trans. Commun.
Hsiu-Chi Chang, Hsie-Chia Chang
2014 — conf
Iterative multi-step decoding for a class of multi-step majority-logic decodable cyclic codes.
ISTC
Hsiu-Chi Chang, Hsie-Chia Chang
2013 J jnl
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis.
IEEE J. Solid State Circuits
Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
2013 — conf
A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine.
ISSCC
Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang
2013 — conf
Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes.
WCSP
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
2013 J jnl
An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes.
IEEE Commun. Lett.
Hsiu-Chi Chang, Chih-Lung Chen, Hsie-Chia Chang
2013 — conf
An area-efficient BCH codec with echelon scheduling for NAND flash applications.
ICC
Chi-Heng Yang, Yi-Hsun Chen, Hsie-Chia Chang
2013 J jnl
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation.
IEEE Trans. Very Large Scale Integr. Syst.
Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
2013 J jnl
Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection.
IEEE Trans. Multim.
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, John K. Zao, Hsie-Chia Chang
2013 J jnl
Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes.
IEEE Commun. Lett.
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
2013 — conf
Processor with side-channel attack resistance.
ISSCC
Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee
2012 J jnl
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder.
IEEE J. Solid State Circuits
Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee
2012 J jnl
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits
Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
2012 J jnl
A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine.
IEEE Trans. Circuits Syst. II Express Briefs
Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
2012 Misc conf
A fully parallel BCH codec with double error correcting capability for NOR flash applications.
ICASSP
Chia-Ching Chu, Yi-Min Lin, Chi-Heng Yang, Hsie-Chia Chang
2012 — conf
A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories.
VLSI-DAT
Yi-Hsun Chen, Chi-Heng Yang, Hsie-Chia Chang
2012 C conf
A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance.
ISCAS
Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee
2012 — conf
A low cost DPA-resistant 8-bit AES core based on ring oscillators.
VLSI-DAT
Hsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
2012 A conf
An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor.
CHES
Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee
2012 J jnl
An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor.
IEEE Trans. Circuits Syst. II Express Briefs
Jen-Wei Lee, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee
2012 C conf
An improved LT encoding scheme with extended chain lengths.
ISITA
Kuo-Kuang Yen, Chih-Lung Chen, Hsie-Chia Chang
2012 — conf
Non-repetitive encoding with increased degree-1 encoding symbols for LT codes.
APCCAS
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
2012 C conf
Stochastic decoding for LDPC convolutional codes.
ISCAS
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2011 — conf
A 2.56 Gb/s soft RS (255, 239) decoder chip for optical communication systems.
ESSCIRC
Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
2011 — conf
A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence.
ESSCIRC
Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee
2011 J jnl
A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices.
IEEE Trans. Circuits Syst. II Express Briefs
Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee
2011 C conf
A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit.
ISCAS
Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
2011 J jnl
High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver.
IEEE Trans. Circuits Syst. I Regul. Pap.
Cheng-Chi Wong, Hsie-Chia Chang
2010 J jnl
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System.
IEEE J. Solid State Circuits
Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2010 — conf
A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance.
ESSCIRC
Jen-Wei Lee, Yao-Lin Chen, Chih-Yeh Tseng, Hsie-Chia Chang, Chen-Yi Lee
2010 J jnl
A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs
Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
2010 J jnl
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder.
J. Low Power Electron.
Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang
2010 — conf
A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique.
APCCAS
Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee
2010 C conf
A multiple code-rate turbo decoder based on reciprocal dual trellis architecture.
ISCAS
Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
2010 C conf
An improved soft BCH decoder with one extra error compensation.
ISCAS
Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
2010 J jnl
Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System.
IEEE Trans. Circuits Syst. II Express Briefs
Cheng-Chi Wong, Hsie-Chia Chang
2010 J jnl
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.
IEEE J. Solid State Circuits
Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
2009 — conf
A 0.92mm
CICC
Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
2009 — conf
A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit.
ESSCIRC
Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
2009 — conf
A 11.5-Gbps LDPC decoder based on CP-PEG code construction.
ESSCIRC
Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, Chen-Yi Lee
2009 J jnl
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee
2009 J jnl
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.
IEEE Trans. Circuits Syst. II Express Briefs
Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
2008 J jnl
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications.
IEEE J. Solid State Circuits
Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
2008 — conf
Early-Pruned K-Best Sphere Decoding Algorithm Based on Radius Constraints.
ICC
Yi Hsuan Wu, Yu Ting Liu, Hsiu-Chi Chang, Yen-Chin Liao, Hsie-Chia Chang
2008 C conf
Multi-mode message passing switch networks applied for QC-LDPC decoder.
ISCAS
Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua
2008 C conf
Structured LDPCcodes with low error floor based on PEG tanner graphs.
ISCAS
Yi-Kai Lin, Chin-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang
2007 — conf
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver.
CICC
Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su
2007 — conf
Low-complexity Prediction Techniques of K-best Sphere Decoding for MIMO Systems.
SiPS
Hsiu-Chi Chang, Yen-Chin Liao, Hsie-Chia Chang
2007 J jnl
Self-Compensation Technique for Simplified Belief-Propagation Algorithm.
IEEE Trans. Signal Process.
Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, Chih-Wei Liu
2006 J jnl
A low power turbo/Viterbi decoder for 3GPP2 applications.
IEEE Trans. Very Large Scale Integr. Syst.
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
2006 C conf
A self-compensation fixed-width booth multiplier and its 128-point FFT applications.
ISCAS
Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang
2006 — conf
Carry Estimation for Two's Complement Fixed-Width Multipliers.
SiPS
Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu
2005 — conf
A 3.33Gb/s (1200,720) low-density parity check code decoder.
ESSCIRC
Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee
2005 J jnl
Design of a power-reduction Viterbi decoder for WLAN applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
2004 — conf
A dual mode channel decoder for 3GPP2 mobile wireless communications.
ESSCIRC
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
2004 — conf
A power and area efficient multi-mode FEC processor.
ISCAS (2)
Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
2004 — conf
Multi-level memory systems using error control codes.
ISCAS (2)
Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang
2003 J jnl
A Low-Power Design for Reed-Solomon Decoders.
J. Circuits Syst. Comput.
Hsie-Chia Chang, Chen-Yi Lee
2001 J jnl
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications.
IEEE J. Solid State Circuits
Hsie-Chia Chang, C. Bernard Shung, Chen-Yi Lee
2001 — conf
An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm.
ISCAS (2)
Hsie-Chia Chang, Chen-Yi Lee
1999 J jnl
New serial architecture for the Berlekamp-Massey algorithm.
IEEE Trans. Commun.
Hsie-Chia Chang, C. Bernard Shung
1998 — conf
A (208, 192;8) Reed-Solomon decoder for DVD application.
ICC
Hsie-Chia Chang, C. Bernard Shung