Hsiao-Hsuan Liu

12 papers A* 1A 1Journal 8Unranked 2
YearRankTypeTitle / Venue / Authors
2025 J jnl
Interconnect/Memory Co-Design and Co-Optimization Using Differential Transmission Lines.
IEEE Trans. Very Large Scale Integr. Syst.
Zhenlin Pei, Hsiao-Hsuan Liu, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Prashant Dubey, Chenyun Pan
2025 J jnl
System Scenario-Based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes.
ACM Trans. Embed. Comput. Syst.
Mahta Mayahinia, Tommaso Marinelli, Zhenlin Pei, Hsiao-Hsuan Liu, Chenyun Pan, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori
2024 J jnl
Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes.
IEEE Embed. Syst. Lett.
Mahta Mayahinia, Tommaso Marinelli, Zhenlin Pei, Hsiao-Hsuan Liu, Chenyun Pan, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori
2024 A* conf
Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning.
DAC
Lucas Huijbregts, Hsiao-Hsuan Liu, Paul Detterer, Said Hamdioui, Amirreza Yousefzadeh, Rajendra Bishnoi
2024 J jnl
Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning.
CoRR
Lucas Huijbregts, Hsiao-Hsuan Liu, Paul Detterer, Said Hamdioui, Amirreza Yousefzadeh, Rajendra Bishnoi
2024 J jnl
Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsiao-Hsuan Liu, Carlo Gilardi, Shairfe Muhammad Salahuddin, Zhenlin Pei, Pieter Schuddinck, Yang Xiang, Pieter Weckx, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert, Chenyun Pan, Subhasish Mitra, Francky Catthoor
2024 J jnl
Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhenlin Pei, Hsiao-Hsuan Liu, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Dawit Burusie Abdi, James Myers, Chenyun Pan
2023 A conf
Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes.
DATE
Mahta Mayahinia, Hsiao-Hsuan Liu, Subrat Mishra, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori
2023 — conf
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access.
ISQED
Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Shairfe Muhammad Salahuddin, Francky Catthoor, Zsolt Tokei, Chenyun Pan
2023 — conf
Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect.
ACM Great Lakes Symposium on VLSI
Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Chenyun Pan
2022 J jnl
Energy-efficient In-Memory Address Calculation.
ACM Trans. Archit. Code Optim.
Amirreza Yousefzadeh, Jan Stuijt, Martijn Hijdra, Hsiao-Hsuan Liu, Anteneh Gebregiorgis, Abhairaj Singh, Said Hamdioui, Francky Catthoor
2015 J jnl
Physical Infrastructure Assessment for Emergency Medical Response.
J. Comput. Civ. Eng.
Hsiao-Hsuan Liu, Albert Y. Chen, Chun-Yi Dai, Wei-Zen Sun