Hsiang-Yun Cheng

37 papers A* 10A 9B 2C 3Misc 1Journal 7Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning. ASP-DAC Hao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Andy Wu
2025	A*	`conf`	Energy-Efficient Large-Scale Vector Similarity Search in NAND-Flash via Hybrid Matching. DAC Chih-Yu Hu, Chi-Tse Huang, Hao-Wei Chiang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Andy Wu
2025	A	`conf`	Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge Devices. DATE Jing-Jia Hung, Yi-Jung Chen, Hsiang-Yun Cheng, Hsu Kao, Chia-Lin Yang
2025	—	`conf`	In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence Analysis. ASP-DAC You-Kai Zheng, Ming-Liang Wei, Hsiang-Yun Cheng, Chia-Lin Yang, Ming-Hsiang Tsai, Chia-Chun Chien, Yuan-Hao Zhong, Po-Hao Tseng, Hsiang-Pang Li
2025	—	`conf`	ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis. ASP-DAC Tsung-Yu Liu, Yen-An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng
2025	A*	`conf`	Segmented Angular Pre-Processing for Accurate and Efficient In-Memory Vector Similarity Search. DAC Chi-Tse Huang, Jen-Chieh Wang, Hsiang-Yun Cheng, An-Yeu Andy Wu
2024	A	`conf`	BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network. DATE Chi-Tse Huang, Cheng-Yang Chang, Hsiang-Yun Cheng, An-Yeu Wu
2024	J	`jnl`	Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning. CoRR Hao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Wu
2024	A*	`conf`	ReAIM: A ReRAM-based Adaptive Ising Machine for Solving Combinatorial Optimization Problems. ISCA Hao-Wei Chiang, Chin-Fu Nien, Hsiang-Yun Cheng, Kuei-Po Huang
2024	A	`conf`	ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis. DATE Tsung-Yu Liu, Yen-An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng
2023	Misc	`conf`	Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng
2023	A*	`conf`	Tensor Movement Orchestration in Multi-GPU Training Systems. HPCA Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang
2022	J	`jnl`	DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators. ACM Trans. Embed. Comput. Syst. Wei-Ting Lin, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, Chin-Fu Nien
2022	A*	`conf`	Efficient Bad Block Management with Cluster Similarity. HPCA Jui-Nan Yen, Yao-Ching Hsieh, Cheng-Yu Chen, Tseng-Yi Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo
2022	—	`conf`	Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging. NVMSA Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang, Bo-Rong Lin, Hsiang-Pang Li
2022	A	`conf`	RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment. DATE Ting Wu, Chin-Fu Nien, Kuang-Chao Chou, Hsiang-Yun Cheng
2022	C	`conf`	Retinex Based on Weaken Factor with Truncated AGCWD for Backlight Image Enhancement. ICCE He-Sheng Chou, Hsiang-Yun Cheng, Jun-Xiang Qiu, Tsun-Kuang Chi, Tsung-Yi Chen, Shin-Lun Chen
2022	—	`conf`	This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator. ASP-DAC Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai
2021	B	`conf`	Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning. ISPASS Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-wei Huang
2021	A	`conf`	Future Computing Platform Design: A Cross-Layer Design Approach. DATE Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo
2021	A*	`conf`	RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration. DAC Chen-Yang Tsai, Chin-Fu Nien, Tz-Ching Yu, Hung-Yu Yeh, Hsiang-Yun Cheng
2021	C	`conf`	ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator. ICCD Yi-Jou Hsiao, Chin-Fu Nien, Hsiang-Yun Cheng
2020	A	`conf`	GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing. DATE Chin-Fu Nien, Yi-Jou Hsiao, Hsiang-Yun Cheng, Cheng-yu Wen, Ya-Cheng Ko, Che-Ching Lin
2019	A*	`conf`	Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. ISCA Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li
2019	J	`jnl`	TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration. IEEE Trans. Computers Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang
2019	A	`conf`	The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper. ICCAD Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang
2018	A	`conf`	DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. ICCAD Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang
2018	J	`jnl`	LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling. CoRR Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang
2017	B	`conf`	Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. ISPASS Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung
2017	J	`jnl`	Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. IEEE Comput. Archit. Lett. Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang
2016	C	`conf`	Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell. ISCAS Meng-Fan Chang, Ching-Hao Chuang, Yen-Ning Chiang, Shyh-Shyuan Sheu, Chia-Chen Kuo, Hsiang-Yun Cheng, John Sampson, Mary Jane Irwin
2016	A*	`conf`	LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches. ISCA Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie
2015	J	`jnl`	Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference. ACM Trans. Design Autom. Electr. Syst. Hsiang-Yun Cheng, Mary Jane Irwin, Yuan Xie
2015	A*	`conf`	Core vs. uncore: the heart of darkness. DAC Hsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin
2015	J	`jnl`	EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors. ACM Trans. Archit. Code Optim. Hsiang-Yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie
2014	A	`conf`	EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors. ISLPED Hsiang-Yun Cheng, Matthew Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie
2010	A*	`conf`	Memory Latency Reduction via Thread Throttling. MICRO Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang