Hsiang-Hui Chang

15 papers Journal 9Unranked 6
YearRankTypeTitle / Venue / Authors
2013 J jnl
A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM.
IEEE J. Solid State Circuits
Tzung-Han Wu, Hsiang-Hui Chang, Shin-Fu Chen, Chinq-Shiun Chiu, Li-Shin Lai, Chi-Hsueh Wang, Song-Yu Yang, Ta-Hsin Lin, Jhy-Rong Chen, Hung-Chieh Tsai, Chi-Yao Yu, Sheng-Yuan Su, Tai-Yuan Yu, Chieh-Chuan Chin, Guang-Kaai Dehng, Augusto Marques, Caiyi Wang, George Chien
2011 — conf
A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS.
A-SSCC
Lan-Chou Cho, Hsiang-Hui Chang, Augusto Marques, Albert Yang, Chinq-Shiun Chiu, Guang-Kaai Dehng
2011 J jnl
A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC.
IEEE J. Solid State Circuits
Chi-Yao Yu, Ivan Siu-Chuang Lu, Yen-Horng Chen, Lan-Chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, George Chien
2009 J jnl
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes.
IEEE J. Solid State Circuits
Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang
2008 — conf
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE.
ISSCC
Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh
2008 — conf
A fractional spur reduction technique for RF TDC-based all digital PLLs.
ESSCIRC
Ping-Ying Wang, Hsiang-Hui Chang, Jing-Hong Conan Zhan
2008 — conf
An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability.
CICC
Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh
2006 J jnl
A 0.7-2-GHz self-calibrated multiphase delay-locked loop.
IEEE J. Solid State Circuits
Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, Shen-Iuan Liu
2005 J jnl
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop.
IEEE J. Solid State Circuits
Hsiang-Hui Chang, Shen-Iuan Liu
2004 J jnl
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu
2003 J jnl
A fast locking and low jitter delay-locked loop using DHDL.
IEEE J. Solid State Circuits
Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu
2003 — conf
A shifted-averaging VCO with precise multiphase outputs and low jitter operation.
ESSCIRC
Hsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu
2003 J jnl
A spread-spectrum clock generator with triangular modulation.
IEEE J. Solid State Circuits
Hsiang-Hui Chang, I-Hui Hua, Shen-Iuan Liu
2002 — conf
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay.
CICC
Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu
2002 J jnl
A wide-range delay-locked loop with a fixed latency of one clock cycle.
IEEE J. Solid State Circuits
Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu