Hritam Dutta - RankMe

23 papers A 2B 1Journal 4Unranked 15

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Trans. High Perform. Embed. Archit. Compil. Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich
2011	—	`—`	Synthesis and exploration of loop accelerators for systems-on-a-chip. Hritam Dutta
2010	—	`conf`	Modeling and synthesis of communication subsystems for loop accelerator pipelines. ASAP Hritam Dutta, Frank Hannig, Moritz Schmid, Joachim Keinert
2009	J	`jnl`	A holistic approach for tightly coupled reconfigurable parallel processors. Microprocess. Microsystems Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier
2009	—	`conf`	Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. ASAP Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich
2009	—	`conf`	Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. SAMOS Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich
2009	—	`conf`	Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ASAP Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich
2009	A	`conf`	Model-based synthesis and optimization of static multi-rate image processing algorithms. DATE Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich
2009	—	`conf`	Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS Frank Hannig, Hritam Dutta, Jürgen Teich
2009	—	`conf`	Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS Hritam Dutta, Frank Hannig, Jürgen Teich
2008	B	`conf`	Coarse-grained reconfiguration. FPL Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008	—	`conf`	PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich
2007	—	`conf`	A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet
2007	J	`jnl`	Efficient control generation for mapping nested loop programs onto processor arrays. J. Syst. Archit. Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich
2007	—	`conf`	Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
2006	—	`conf`	A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger
2006	—	`conf`	Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS Hritam Dutta, Frank Hannig, Jürgen Teich
2006	—	`conf`	Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC Hritam Dutta, Frank Hannig, Jürgen Teich
2006	J	`jnl`	Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. Int. J. Embed. Syst. Frank Hannig, Hritam Dutta, Jürgen Teich
2005	—	`conf`	Automatic FIR Filter Generation for FPGAs. SAMOS Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich
2005	—	`conf`	Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys
2004	A	`conf`	Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS Frank Hannig, Hritam Dutta, Jürgen Teich
2004	—	`conf`	Regular mapping for coarse-grained reconfigurable architectures. ICASSP (5) Frank Hannig, Hritam Dutta, Jürgen Teich