Hratch Mangassarian

15 papers A 7B 1Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2014 J jnl
Debugging RTL Using Structural Dominance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hratch Mangassarian, Bao Le, Andreas G. Veneris
2012 J jnl
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm
2012 A conf
Non-solution implications using reverse domination in a modern SAT-based debugging environment.
DATE
Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris
2012 — conf
On error tolerance and Engineering Change with Partially Programmable Circuits.
ASP-DAC
Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita
2011 A conf
Debugging with dominance: On-the-fly RTL debug solution implications.
ICCAD
Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour
2010 A conf
Leveraging dominators for preprocessing QBF.
DATE
Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus
2010 J jnl
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test.
IEEE Trans. Computers
Hratch Mangassarian, Andreas G. Veneris, Marco Benedetti
2008 A conf
A succinct memory model for automated design debugging.
ICCAD
Brian Keng, Hratch Mangassarian, Andreas G. Veneris
2008 J jnl
QBF-Based Formal Verification: Experience and Perspectives.
J. Satisf. Boolean Model. Comput.
Marco Benedetti, Hratch Mangassarian
2007 J jnl
A general framework for subjective information extraction from unstructured English text.
Data Knowl. Eng.
Hratch Mangassarian, Hassan Artail
2007 A conf
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test.
ICCAD
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith
2007 B conf
Improved Design Debugging Using Maximum Satisfiability.
FMCAD
Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah
2007 A conf
Maximum circuit activity estimation using pseudo-boolean satisfiability.
DATE
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
2007 — conf
Trace Compaction using SAT-based Reachability Analysis.
ASP-DAC
Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian
2005 A conf
On Statistical Timing Analysis with Inter- and Intra-Die Variations.
DATE
Hratch Mangassarian, Mohab Anis