Hoyoung Yoo

34 papers Misc 1Journal 15Unranked 18
YearRankTypeTitle / Venue / Authors
2025 J jnl
Efficient Doppler Frequency Simulator for Multifrequency.
IEEE Trans. Instrum. Meas.
Sukjae Yoon, Kyoduk Ku, Hoyoung Yoo
2024 — conf
Efficient CRC-BCH Unified Encoder for Global Positioning System.
ICEIC
Yongtaek Hwang, Jiwoo Hwang, Yuseok Lee, Hoyoung Yoo
2024 J jnl
Hybrid Precision Floating-Point (HPFP) Selection to Optimize Hardware-Constrained Accelerator for CNN Training.
Sensors
Muhammad Junaid, Hayotjon Aliev, Sangbo Park, HyungWon Kim, Hoyoung Yoo, Sanghoon Sim
2024 — conf
Implementation of Activation Functions using various approximation methods.
ISOCC
Jiho Park, Geon Shin, Hoyoung Yoo
2024 — conf
Physical Unclonable Function Using Programmable Delay Lines.
ICEIC
Jiho Park, Hee-Hun Yang, Donghun Lee, Hoyoung Yoo
2023 — conf
An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency.
ICEIC
Byeong Yong Kong, Hoyoung Yoo, Youngjoo Lee
2023 — conf
Practical Analysis of Xilinx FPGAs' Bitstream Encryption.
ICEIC
Eunchae Lee, Soyeon Choi, Jiho Park, Sungkyun Shin, Hoyoung Yoo
2023 — conf
Quantitative Analysis of Various 2D CNN Structures based on Dataflow.
ICEIC
Sangwon Lee, Jiho Park, Jeongho Kim, Yongtaek Hwang, Soyeon Choi, Hoyoung Yoo
2022 — conf
Implementation of Aurora Interface using SFP+ Transceiver.
ISOCC
Sungkyun Shin, Soyeon Choi, Eunchae Lee, Songyeon Lee, Hoyoung Yoo
2022 J jnl
S-Box Attack Using FPGA Reverse Engineering for Lightweight Cryptography.
IEEE Internet Things J.
Nari Im, Soyeon Choi, Hoyoung Yoo
2021 — conf
Analysis of Ring-Oscillator-based True Random Number Generator on FPGAs.
ICEIC
Soyeon Choi, Yerin Shin, Hoyoung Yoo
2021 — conf
Area-Efficient On-the-Fly Code Generator for BDS B1C Receivers.
ICEIC
Jiwoon Park, Gwang Hee Jo, Jinseok Kim, Hoyoung Yoo
2021 — conf
Configurable Digital Pulse Generator for Neuromorphic Devices.
ICEIC
Sungryoung Lee, Hoyoung Yoo
2021 — conf
FPGA Design Duplication based on the Bitstream Extraction.
ISOCC
Soyeon Choi, Nari Im, Hoyoung Yoo
2021 J jnl
Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism.
IEEE Trans. Very Large Scale Integr. Syst.
Dongyun Kam, Hoyoung Yoo, Youngjoo Lee
2020 — conf
Extraction of ROM Data from Bitstream in Xilinx FPGA.
ISOCC
Soyeon Choi, Jieun Yeo, Hoyoung Yoo
2019 — conf
On-demand Syndrome Calculation for BCH decoding.
ICEIC
Hyeonkyu Kim, Soyeon Choi, Hoyoung Yoo
2018 — conf
Hybrid Decoding for Polar Codes.
ISOCC
Soyeon Choi, Hoyoung Yoo
2018 J jnl
Resource usage of LTE networks for machine-to-Machine group communications: Modeling and analysis.
Comput. Electr. Eng.
Eunmi Chu, Hoyoung Yoo, Bang Chul Jung
2016 J jnl
Efficient Pruning for Successive-Cancellation Decoding of Polar Codes.
IEEE Commun. Lett.
Hoyoung Yoo, In-Cheol Park
2016 J jnl
Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Byeong Yong Kong, Hoyoung Yoo, In-Cheol Park
2016 J jnl
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Jihyuck Jo, Hoyoung Yoo, In-Cheol Park
2016 J jnl
Low-Power Parallel Chien Search Architecture Using a Two-Step Approach.
IEEE Trans. Circuits Syst. II Express Briefs
Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
2015 J jnl
Efficient Parallel Architecture for Linear Feedback Shift Registers.
IEEE Trans. Circuits Syst. II Express Briefs
Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
2015 J jnl
Partially Parallel Encoder Architecture for Long Polar Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Hoyoung Yoo, In-Cheol Park
2014 — conf
7.3 Gb/s universal BCH encoder and decoder for SSD controllers.
ASP-DAC
Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
2014 J jnl
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives.
IEEE Trans. Very Large Scale Integr. Syst.
Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park
2013 J jnl
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.
IEEE J. Solid State Circuits
Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park
2013 — conf
A 3Gb/s 2.08mm
ASP-DAC
Youngjoo Lee, Hoyoung Yoo, In-Cheol Park
2013 J jnl
Area-Efficient Multimode Encoding Architecture for Long BCH Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park
2012 — conf
6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers.
ISSCC
Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park
2012 — conf
Low-latency area-efficient decoding architecture for shortened reed-solomon codes.
ISOCC
Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
2012 Misc conf
Small-area parallel syndrome calculation for strong BCH decoding.
ICASSP
Youngjoo Lee, Hoyoung Yoo, In-Cheol Park
2011 J jnl
Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization.
IEEE Trans. Circuits Syst. II Express Briefs
Youngjoo Lee, Hoyoung Yoo, In-Cheol Park