Hossein Valavi

13 papers A 1Misc 2Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2022 J jnl
Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing.
IEEE J. Solid State Circuits
Hongyang Jia, Murat Ozatay, Yinqi Tang, Hossein Valavi, Rakshit Pathak, Jinseok Lee, Naveen Verma
2021 — conf
A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing.
ISSCC
Hongyang Jia, Murat Ozatay, Yinqi Tang, Hossein Valavi, Rakshit Pathak, Jinseok Lee, Naveen Verma
2021 — conf
Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs.
VLSI Circuits
Jinseok Lee, Hossein Valavi, Yinqi Tang, Naveen Verma
2020 J jnl
A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing.
IEEE J. Solid State Circuits
Hongyang Jia, Hossein Valavi, Yinqi Tang, Jintao Zhang, Naveen Verma
2020 — —
Hardware acceleration to address the costs of data movement
Hossein Valavi
2020 A conf
Revisiting the Landscape of Matrix Factorization.
AISTATS
Hossein Valavi, Sulin Liu, Peter J. Ramadge
2020 J jnl
The Landscape of Matrix Factorization Revisited.
CoRR
Hossein Valavi, Sulin Liu, Peter J. Ramadge
2019 J jnl
A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute.
IEEE J. Solid State Circuits
Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma
2019 — conf
A Programmable Embedded Microprocessor for Bit-scalable In-memory Computing.
Hot Chips Symposium
Hongyang Jia, Hossein Valavi, Yinqi Tang, Jintao Zhang, Naveen Verma
2019 Misc conf
Multi-dataset Low-rank Matrix Factorization.
CISS
Hossein Valavi, Peter J. Ramadge
2018 J jnl
A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computing.
CoRR
Hongyang Jia, Yinqi Tang, Hossein Valavi, Jintao Zhang, Naveen Verma
2018 — conf
A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement.
VLSI Circuits
Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma
2018 Misc conf
An Upper-Bound on the Required Size of a Neural Network Classifier.
ICASSP
Hossein Valavi, Peter J. Ramadge