Hossein Asadi - RankMe

112 papers A* 2A 14B 5C 4Misc 1Journal 73Unranked 13

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation. CoRR Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2026	J	`jnl`	ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches. CoRR Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2026	J	`jnl`	Smart Prediction of I/O Accesses in Enterprise Workloads to Accelerate Data Serving During Array Reconstruction. IEEE Comput. Archit. Lett. Mohammad M. Gharaguzlo, Mohammadamin Ajdari, Hossein Asadi
2026	J	`jnl`	Towards Scalable Storage Architectures for GPU Clusters Running Large Language Models. Proc. ACM Meas. Anal. Comput. Syst. Ali Sedaghatgoo, Reza Salkhordeh, André Brinkmann, Hossein Asadi
2025	J	`jnl`	3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison. CoRR Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2025	J	`jnl`	A Reliability-Aware Replacement Policy for STT-MRAM Caches in Server-Class Processors. IEEE Trans. Reliab. Abdollah Mohammadi, Elham Cheshmikhani, Hossein Asadi
2025	J	`jnl`	ELICA: Efficient and Load Balanced I/O Cache Architecture for Hyperconverged Infrastructures. IEEE Trans. Parallel Distributed Syst. Mostafa Kishani, Sina Ahmadi, Saba Ahmadian, Reza Salkhordeh, Zdenek Becvar, Onur Mutlu, André Brinkmann, Hossein Asadi
2025	C	`conf`	Enhancing mmap scalability by saving TLB shootdowns during page recycling. PDP Frederic Schimmelpfennig, André Brinkmann, Hossein Asadi, Reza Salkhordeh
2025	J	`jnl`	I/O-ETEM: An I/O-Aware Approach for Estimating Execution Time of Machine Learning Workloads. IEEE Comput. Archit. Lett. Elham Adibi, Mohammadamin Ajdari, Pouria Arefijamal, Amirsaeed Ahmadi-Tonekaboni, Hossein Asadi
2025	B	`conf`	No Time to Halt: In-Situ Analysis for Large-Scale Data Processing via Virtual Snapshotting. EDBT Reza Salkhordeh, Felix Martin Schuhknecht, Hossein Asadi, Steffen Eiden, André Brinkmann
2024	—	`conf`	A Hierarchical Modeling Approach for Assessing the Reliability and Performability of Burst Buffers. ARCS Eric Borba, Reza Salkhordeh, Salim Mimouni, Eduardo Tavares, Paulo Maciel, Hossein Asadi, André Brinkmann
2024	J	`jnl`	Empirical Architectural Analysis on Performance Scalability of Petascale All-Flash Storage Systems. IEEE Comput. Archit. Lett. Mohammadamin Ajdari, Behrang Montazerzohour, Kimia Abdi, Hossein Asadi
2024	J	`jnl`	From SSDs Back to HDDs: Optimizing VDO to Support Inline Deduplication and Compression for HDDs as Primary Storage Media. ACM Trans. Storage Patrick Raaf, André Brinkmann, Eric Borba, Hossein Asadi, Sai Narasimhamurthy, John Bent, Mohamad El-Batal, Reza Salkhordeh
2024	J	`jnl`	HybRAID: A High-Performance Hybrid RAID Storage Architecture for Write-Intensive Applications in All-Flash Storage Systems. IEEE Trans. Parallel Distributed Syst. Maryam Karimi, Reza Salkhordeh, André Brinkmann, Hossein Asadi
2024	J	`jnl`	Joint Optimization of Communication and Storage Latencies for Vehicular Edge Computing. IEEE Trans. Intell. Transp. Syst. Mostafa Kishani, Zdenek Becvar, Mohammadsaleh Nikooroo, Hossein Asadi
2024	J	`jnl`	Skip TLB flushes for reused pages within mmap's. CoRR Frederic Schimmelpfennig, André Brinkmann, Hossein Asadi, Reza Salkhordeh
2023	J	`jnl`	PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era. IEEE Trans. Very Large Scale Integr. Syst. Zeinab Seifoori, Behzad Omidi, Hossein Asadi
2023	—	`conf`	Re-architecting I/O Caches for Emerging Fast Storage Devices. ASPLOS (3) Mohammadamin Ajdari, Pouria Peykani Sani, Amirhossein Moradi, Masoud Khanalizadeh Imani, Amir Hossein Bazkhanei, Hossein Asadi
2022	J	`jnl`	3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison. IEEE Trans. Computers Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2022	J	`jnl`	A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. CoRR Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2022	—	`conf`	An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems. SIGMETRICS (Abstracts) Mohammadamin Ajdari, Patrick Raaf, Mostafa Kishani, Reza Salkhordeh, Hossein Asadi, André Brinkmann
2022	J	`jnl`	An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems. Proc. ACM Meas. Anal. Comput. Syst. Mohammadamin Ajdari, Patrick Raaf, Mostafa Kishani, Reza Salkhordeh, Hossein Asadi, André Brinkmann
2022	J	`jnl`	CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers. CoRR Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi
2022	J	`jnl`	CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers. IEEE Trans. Parallel Distributed Syst. Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi
2022	J	`jnl`	Quick Generation of SSD Performance Models Using Machine Learning. IEEE Trans. Emerg. Top. Comput. Mojtaba Tarihi, Soheil Azadvar, Arash Tavakkol, Hossein Asadi, Hamid Sarbazi-Azad
2022	J	`jnl`	RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks. IEEE Trans. Emerg. Top. Comput. Shahriar Ebrahimi, Reza Salkhordeh, Seyed Ali Osia, Ali Taheri, Hamid R. Rabiee, Hossein Asadi
2022	—	`conf`	Reducing Storage and Communication Latencies in Vehicular Edge Cloud. EuCNC Mostafa Kishani, Zdenek Becvar, Mohammadsaleh Nikooroo, Hossein Asadi
2022	J	`jnl`	TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. CoRR Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi, Hossein Asadi
2021	J	`jnl`	A Modeling Framework for Reliability of Erasure Codes in SSD Arrays. CoRR Mostafa Kishani, Saba Ahmadian, Hossein Asadi
2021	J	`jnl`	Dependability Analysis of Data Storage Systems in Presence of Soft Errors. CoRR Mostafa Kishani, Mehdi B. Tahoori, Hossein Asadi
2021	J	`jnl`	ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms. CoRR Saba Ahmadian, Reza Salkhordeh, Onur Mutlu, Hossein Asadi
2021	J	`jnl`	ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms. IEEE Trans. Parallel Distributed Syst. Saba Ahmadian, Reza Salkhordeh, Onur Mutlu, Hossein Asadi
2021	J	`jnl`	Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems. IEEE Trans. Emerg. Top. Comput. Saba Ahmadian, Farhad Taheri, Hossein Asadi
2021	—	`conf`	PADSA: Priority-Aware Block Data Storage Architecture for Edge Cloud Serving Autonomous Vehicles. VNC Mostafa Kishani, Zdenek Becvar, Hossein Asadi
2021	J	`jnl`	RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks. CoRR Shahriar Ebrahimi, Reza Salkhordeh, Seyed Ali Osia, Ali Taheri, Hamidreza Rabiee, Hossein Asadi
2021	J	`jnl`	Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing. IEEE Access Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic
2020	J	`jnl`	A Modeling Framework for Reliability of Erasure Codes in SSD Arrays. IEEE Trans. Computers Mostafa Kishani, Saba Ahmadian, Hossein Asadi
2020	J	`jnl`	A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. IEEE Trans. Reliab. Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2020	A	`conf`	STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation. DATE Mostafa Hadizadeh, Elham Cheshmikhani, Hossein Asadi
2019	—	`conf`	A Machine Learning Approach for Power Gating the FPGA Routing Network. FPT Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic
2019	J	`jnl`	A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs. J. Electron. Test. Omid Ranjbar, Siavash Bayat Sarmadi, Fatemeh Pooyan, Hossein Asadi
2019	J	`jnl`	An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. CoRR Reza Salkhordeh, Onur Mutlu, Hossein Asadi
2019	J	`jnl`	An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. IEEE Trans. Computers Reza Salkhordeh, Onur Mutlu, Hossein Asadi
2019	J	`jnl`	An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs. IEEE Trans. Parallel Distributed Syst. Reza Salkhordeh, Mostafa Hadizadeh, Hossein Asadi
2019	J	`jnl`	An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sajjad Tamimi, Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi
2019	J	`jnl`	Dependability Analysis of Data Storage Systems in Presence of Soft Errors. IEEE Trans. Reliab. Mostafa Kishani, Mehdi Baradaran Tahoori, Hossein Asadi
2019	A	`conf`	Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation. DATE Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2019	J	`jnl`	Estimating and Mitigating Aging Effects in Routing Network of FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi
2019	J	`jnl`	Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems. CoRR Saba Ahmadian, Farhad Taheri, Hossein Asadi
2019	A	`conf`	LBICA: A Load Balancer for I/O Cache Architectures. DATE Saba Ahmadian, Reza Salkhordeh, Hossein Asadi
2019	—	`conf`	ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches. ASP-DAC Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2019	J	`jnl`	TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. IEEE Trans. Computers Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi, Hossein Asadi
2018	J	`jnl`	A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry. IEEE Trans. Circuits Syst. I Regul. Pap. Behnam Khaleghi, Hossein Asadi
2018	J	`jnl`	An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs. CoRR Reza Salkhordeh, Mostafa Hadizadeh, Hossein Asadi
2018	J	`jnl`	An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture. CoRR Reza Salkhordeh, Hossein Asadi
2018	J	`jnl`	Chapter Seven - Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era. Adv. Comput. Zeinab Seifoori, Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi
2018	—	`conf`	ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms. SIGMETRICS (Abstracts) Saba Ahmadian, Onur Mutlu, Hossein Asadi
2018	J	`jnl`	ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms. CoRR Saba Ahmadian, Onur Mutlu, Hossein Asadi
2018	J	`jnl`	ECI-Cache: A High-Endurance and Cost-Efficient I/O Caching Scheme for Virtualized Platforms. Proc. ACM Meas. Anal. Comput. Syst. Saba Ahmadian, Onur Mutlu, Hossein Asadi
2018	J	`jnl`	Evaluating Impact of Human Errors on the Availability of Data Storage Systems. CoRR Mostafa Kishani, Reza Eftekhari, Hossein Asadi
2018	J	`jnl`	Investigating Power Outage Effects on Reliability of Solid-State Drives. CoRR Saba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi, Hossein Asadi
2018	A	`conf`	Investigating power outage effects on reliability of solid-state drives. DATE Saba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi, Hossein Asadi
2018	J	`jnl`	LBICA: A Load Balancer for I/O Cache Architectures. CoRR Saba Ahmadian, Reza Salkhordeh, Hossein Asadi
2018	J	`jnl`	Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems. CoRR Mostafa Kishani, Hossein Asadi
2018	J	`jnl`	Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems. IEEE Trans. Reliab. Mostafa Kishani, Hossein Asadi
2018	J	`jnl`	ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization. IEEE Trans. Parallel Distributed Syst. Reza Salkhordeh, Shahriar Ebrahimi, Hossein Asadi
2018	J	`jnl`	ReCA: an Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization. CoRR Reza Salkhordeh, Shahriar Ebrahimi, Hossein Asadi
2017	A	`conf`	A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era. DATE Zeinab Seifoori, Behnam Khaleghi, Hossein Asadi
2017	A	`conf`	Evaluating impact of human errors on the availability of data storage systems. DATE Mostafa Kishani, Reza Eftekhari, Hossein Asadi
2017	J	`jnl`	PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era. IEEE Trans. Computers Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi
2016	J	`jnl`	A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction. IEEE Trans. Very Large Scale Integr. Syst. Hamed Farbeh, Nooshin Sadat Mirzadeh, Nahid Farhady Ghalaty, Seyed Ghassem Miremadi, Mahdi Fazeli, Hossein Asadi
2016	J	`jnl`	A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization. IEEE Trans. Computers Mojtaba Tarihi, Hossein Asadi, Alireza Haghdoost, Mohammad Arjomand, Hamid Sarbazi-Azad
2016	A	`conf`	An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture. DATE Reza Salkhordeh, Hossein Asadi
2016	J	`jnl`	Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi
2016	J	`jnl`	Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. IEEE Trans. Computers Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad
2016	J	`jnl`	Introduction: Special Section on Architecture of Future Many Core Systems. Microprocess. Microsystems Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad
2016	J	`jnl`	Layout-Based Modeling and Mitigation of Multiple Event Transients. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mojtaba Ebrahimi, Hossein Asadi, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2016	B	`conf`	Stress-aware routing to mitigate aging effects in SRAM-based FPGAs. FPL Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi
2015	J	`jnl`	A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices. IEEE Trans. Very Large Scale Integr. Syst. Sadegh Yazdanshenas, Hossein Asadi, Behnam Khaleghi
2015	B	`conf`	An efficient reconfigurable architecture by characterizing most frequent logic functions. FPL Iman Ahmadpour, Behnam Khaleghi, Hossein Asadi
2015	A*	`conf`	DiskAccel: Accelerating Disk-Based Experiments by Representative Sampling. SIGMETRICS Mojtaba Tarihi, Hossein Asadi, Hamid Sarbazi-Azad
2015	J	`jnl`	FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic. IEEE Embed. Syst. Lett. Behnam Khaleghi, Ali Ahari, Hossein Asadi, Siavash Bayat Sarmadi
2015	J	`jnl`	On endurance and performance of erasure codes in SSD-based storage systems. Microelectron. Reliab. Saeideh Alinezhad Chamazcoti, Ziba Delavari, Seyed Ghassem Miremadi, Hossein Asadi
2015	J	`jnl`	Operating system level data tiering using online workload characterization. J. Supercomput. Reza Salkhordeh, Hossein Asadi, Shahriar Ebrahimi
2014	A	`conf`	A power-efficient reconfigurable architecture using PCM configuration technology. DATE Ali Ahari, Hossein Asadi, Behnam Khaleghi, Mehdi Baradaran Tahoori
2014	J	`jnl`	CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors. Microelectron. Reliab. Hossein Asadi, Alireza Haghdoost, Morteza Ramezani, Nima Elyasi, Amirali Baniasadi
2014	—	`conf`	Emerging Non-Volatile Memory technologies for future low power reconfigurable systems. ReCoSoC Ali Ahari, Hossein Asadi, Mehdi Baradaran Tahoori
2014	J	`jnl`	Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices. IEEE Trans. Circuits Syst. II Express Briefs Sadegh Yazdanshenas, Hossein Asadi
2014	J	`jnl`	Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates. Microelectron. Reliab. Siavash Rezaei, Seyed Ghassem Miremadi, Hossein Asadi, Mahdi Fazeli
2014	B	`conf`	Towards dark silicon era in FPGAs using complementary hard logic design. FPL Ali Ahari, Behnam Khaleghi, Zahra Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori
2013	A*	`conf`	A layout-based approach for multiple event transient analysis. DAC Mojtaba Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori
2013	—	`conf`	CLASS: Combined logic and architectural soft error sensitivity analysis. ASP-DAC Mojtaba Ebrahimi, Liang Chen, Hossein Asadi, Mehdi Baradaran Tahoori
2013	—	`conf`	FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications. ASAP Mohammad Hossein Hajkazemi, Amirali Baniasadi, Hossein Asadi
2013	A	`conf`	FTSPM: A Fault-Tolerant ScratchPad Memory. DSN Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Seyed Ghassem Miremadi, Mahdi Fazeli, Hossein Asadi
2013	J	`jnl`	Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems. IEEE Trans. Very Large Scale Integr. Syst. Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi, Mahdi Fazeli
2012	J	`jnl`	Efficient algorithms to accurately compute derating factors of digital circuits. Microelectron. Reliab. Hossein Asadi, Mehdi Baradaran Tahoori, Mahdi Fazeli, Seyed Ghassem Miremadi
2011	A	`conf`	ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications. DATE Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi
2011	A	`conf`	Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs). DATE Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori
2010	C	`conf`	A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits. DSD Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori
2010	A	`conf`	A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design. DSN Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Seyed Nematollah Ahmadian
2010	J	`jnl`	Soft error modeling and remediation techniques in ASIC designs. Microelectron. J. Hossein Asadi, Mehdi Baradaran Tahoori
2010	C	`conf`	System-Level Vulnerability Estimation for Data Caches. PRDC Alireza Haghdoost, Hossein Asadi, Amirali Baniasadi
2009	J	`jnl`	Obtaining FPGA soft error rate in high performance information systems. Microelectron. Reliab. Mehdi Baradaran Tahoori, Hossein Asadi, Brian Mullins, David R. Kaeli
2007	J	`jnl`	Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs. IEEE Trans. Very Large Scale Integr. Syst. Hossein Asadi, Mehdi Baradaran Tahoori
2007	Misc	`conf`	Case Study: Soft Error Rate Analysis in Storage Systems. VTS Brian Mullins, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli, Kevin Granlund, Rudy Bauer, Scott Romano
2007	—	`conf`	Estimating Error Propagation Probabilities with Bounded Variances. DFT Hossein Asadi, Mehdi Baradaran Tahoori, Chandra Tirumurti
2006	J	`jnl`	Reducing Data Cache Susceptibility to Soft Errors. IEEE Trans. Dependable Secur. Comput. Vilas Sridharan, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli
2006	A	`conf`	Soft error derating computation in sequential circuits. ICCAD Hossein Asadi, Mehdi Baradaran Tahoori
2006	C	`conf`	Soft error hardening for logic-level designs. ISCAS Hossein Asadi, Mehdi Baradaran Tahoori
2006	A	`conf`	Vulnerability analysis of L2 cache elements to single event upsets. DATE Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli
2005	B	`conf`	Balancing Performance and Reliability in the Memory Hierarchy. ISPASS Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli
2005	—	`conf`	Soft Error Modeling and Protection for Sequential Elements. DFT Hossein Asadi, Mehdi Baradaran Tahoori