Hosahalli R. Srinivas

13 papers C 4Misc 3Journal 6
YearRankTypeTitle / Venue / Authors
1999 J jnl
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture.
J. VLSI Signal Process.
Hosahalli R. Srinivas, Keshab K. Parhi
1998 Misc conf
VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay.
VLSI Design
S. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, Marc S. Diamondstein
1997 Misc conf
Half-rate GSM vocoder implementation on a dual mac digital signal processor.
ICASSP
Mohit K. Prasad, Paul D'Arcy, Arup Gupta, Marc S. Diamondstein, Hosahalli R. Srinivas
1997 J jnl
Radix 2 Division with Over-Redundant Quotient Selection.
IEEE Trans. Computers
Hosahalli R. Srinivas, Keshab K. Parhi, Luis A. Montalvo
1995 Misc conf
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.
VLSI Design
W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi
1995 J jnl
A Fast Radix-4 Division Algorithm and Its Architecture.
IEEE Trans. Computers
Hosahalli R. Srinivas, Keshab K. Parhi
1995 C conf
A floating point radix 2 shared division/square root chip.
ICCD
Hosahalli R. Srinivas, Keshab K. Parhi
1994 J jnl
A C-testable carry-free divider.
IEEE Trans. Very Large Scale Integr. Syst.
Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi
1994 C conf
A Fast Radix-4 Division Algorithm.
ISCAS
Hosahalli R. Srinivas, Keshab K. Parhi
1993 C conf
A C-Testable Carry-Free Divider.
ICCD
Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi
1992 J jnl
A fast VLSI adder architecture.
IEEE J. Solid State Circuits
Hosahalli R. Srinivas, Keshab K. Parhi
1992 J jnl
High-speed VLSI arithmetic processor architectures using hybrid number representation.
J. VLSI Signal Process.
Hosahalli R. Srinivas, Keshab K. Parhi
1991 C conf
High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation.
ICCD
Hosahalli R. Srinivas, Keshab K. Parhi