Horácio C. Neto

80 papers B 20C 8Misc 4Journal 21Unranked 27

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Coarse-Grained Reconfigurable Arrays for High-Performance Low-Power Deep Neural Networks on Embedded Devices. DoCEIS João D. Lopes, Horácio C. Neto, José T. de Sousa
2024	J	`jnl`	Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines. ACM Trans. Reconfigurable Technol. Syst. Miguel Reis, Mário P. Véstias, Horácio C. Neto
2024	—	`conf`	LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization. ARC Henrique B. Brum, Mário P. Véstias, Horácio C. Neto
2024	C	`conf`	PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. ARITH José T. de Sousa, João D. Lopes, Micaela Serôdio, Horácio C. Neto, Mário P. Véstias
2023	J	`jnl`	Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. ACM Trans. Reconfigurable Technol. Syst. Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2023	J	`jnl`	Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA. Algorithms Maria Inês Frutuoso, Horácio C. Neto, Mário P. Véstias, Rui Policarpo Duarte
2022	J	`jnl`	A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. Remote. Sens. Helena Cruz, Mário P. Véstias, José Monteiro, Horácio C. Neto, Rui Policarpo Duarte
2022	J	`jnl`	Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias
2022	J	`jnl`	System on Chip (SoC) for Invisible Electrocardiography (ECG) Biometrics. Sensors Francisco Melo, Horácio C. Neto, Hugo Plácido da Silva
2021	J	`jnl`	A Full Featured Configurable Accelerator for Object Detection With YOLO. IEEE Access Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa
2021	J	`jnl`	Configurable Hardware Core for IoT Object Detection. Future Internet Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa
2021	J	`jnl`	Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. Algorithms Mário P. Véstias, Horácio C. Neto
2020	J	`jnl`	A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. IEEE Access Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2020	J	`jnl`	A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocess. Microsystems Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2020	J	`jnl`	Moving Deep Learning to the Edge. Algorithms Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2020	—	`conf`	Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm. ARC Rui Policarpo Duarte, Helena Cruz, Horácio C. Neto
2019	J	`jnl`	Embedded Fault-Tolerant Accelerator Architecture for Synthetic-Aperture Radar Backprojection. J. Aerosp. Inf. Syst. Helena Cruz, Rui Policarpo Duarte, Horácio C. Neto
2019	—	`conf`	Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging. ARC Helena Cruz, Rui Policarpo Duarte, Horácio C. Neto
2019	B	`conf`	Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. FPL Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2019	J	`jnl`	kNN-STUFF: kNN STreaming Unit for Fpgas. IEEE Access João Vieira, Rui Policarpo Duarte, Horácio C. Neto
2018	B	`conf`	An Efficient Exact Fused Dot Product Processor in FPGA. FPL Luís Fiolhais, Horácio C. Neto
2018	—	`conf`	FPGA-based OpenCL Accelerator for Discovering Temporal Patterns in Gene Expression Data Using Biclustering. PBio@EuroMPI Rui Policarpo Duarte, Álvaro Simões, Rui Henriques, Horácio C. Neto
2018	J	`jnl`	Improving the area of fast parallel decimal multipliers. Microprocess. Microsystems Mário P. Véstias, Horácio C. Neto
2018	B	`conf`	Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. FPL Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2018	—	`conf`	Stochastic Processors on FPGAs to Compute Sensor Data Towards Fault-Tolerant IoT Systems. DSC Rui Policarpo Duarte, Horácio C. Neto
2017	J	`jnl`	Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocess. Microsystems Horácio C. Neto, Mário P. Véstias
2017	B	`conf`	K-means clustering on CGRA. FPL João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias
2017	B	`conf`	Parallel dot-products for deep learning on FPGA. FPL Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2016	B	`conf`	Multi-core for K-means clustering on FPGA. FPL Jose Canilho, Mário P. Véstias, Horácio C. Neto
2016	—	`conf`	XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system. ICRC Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias
2015	—	`conf`	A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow. ISVLSI Victor M. Goncalves Martins, Paulo Ricardo Cechelero Villa, Horácio C. Neto, Eduardo Augusto Bezerra
2015	J	`jnl`	Designing Hardware/Software Systems for Embedded High-Performance Computing. CoRR Mário P. Véstias, Rui Policarpo Duarte, Horácio C. Neto
2015	Misc	`conf`	Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions. FCCM Victor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra
2015	B	`conf`	Enhancing stochastic computations via process variation. FPL Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto
2015	—	`conf`	FPGA redundancy recovery based on partial bitstreams for multiple partitions. LATS Victor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra
2015	C	`conf`	Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture. DSD João Pinhão, Wilson José, Horácio C. Neto, Mário P. Véstias
2014	J	`jnl`	A Many-Core Overlay for High-Performance Embedded Computing on FPGAs. CoRR Mário P. Véstias, Horácio C. Neto
2014	B	`conf`	Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. FPL Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias
2014	B	`conf`	Trends of CPU, GPU and FPGA for high-performance computing. FPL Mário P. Véstias, Horácio C. Neto
2013	B	`conf`	A reconfigurable computing architecture using magnetic tunneling junction memories. FPL Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto
2013	B	`conf`	Analysis of matrix multiplication on high density Virtex-7 FPGA. FPL Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias
2013	—	`conf`	Design of a massively parallel computing architecture for dense matrix multiplication. LASCAS Wilson José, Ana Rita Silva, Mário P. Véstias, Horácio C. Neto
2013	—	`conf`	Design of a multiband full-rate ultra-wideband receiver in FPGA. LASCAS Mário P. Véstias, Horácio C. Neto, Helena Sarmento
2013	—	`conf`	Very low resource table-based FPGA evaluation of elementary functions. ReConFig Horácio C. Neto, Mário P. Véstias
2012	—	`conf`	A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory. ReConFig Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto
2012	C	`conf`	Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs. DSD Mário P. Véstias, Horácio C. Neto, Helena Sarmento
2012	—	`conf`	Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions. ICECS Victor Silva, Mário P. Véstias, Horácio C. Neto, Jorge R. Fernandes
2012	C	`conf`	Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm. DSD Mário P. Véstias, Horácio C. Neto
2012	B	`conf`	Sliding block Viterbi decoders in FPGA. FPL Mário P. Véstias, Horácio C. Neto, Helena Sarmento
2011	B	`conf`	Revisiting the Newton-Raphson Iterative Method for Decimal Division. FPL Mário P. Véstias, Horácio C. Neto
2010	—	`conf`	Reconfigurable Circuits Using Magnetic Tunneling Junction Memories. DoCEIS Victor Silva, Jorge R. Fernandes, Horácio C. Neto
2009	C	`conf`	Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. DSD Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias
2009	C	`conf`	Run-Time Reconfigurable Array Using Magnetic RAM. DSD Victor Silva, Luís Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto
2009	—	`conf`	Unbalanced FIFO sorting for FPGA-based systems. ICECS Rui Marcelino, Horácio C. Neto, João M. P. Cardoso
2008	B	`conf`	Decimal multiplier on FPGA using embedded binary multipliers. FPL Horácio C. Neto, Mário P. Véstias
2008	—	`conf`	Multiplier-based double precision floating point divider according to the IEEE-754 standard. ARC Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto
2008	—	`conf`	Sorting Units for FPGA-Based Embedded Systems. DIPES Rui Marcelino, Horácio C. Neto, João M. P. Cardoso
2007	B	`conf`	Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. FPL Mário P. Véstias, Horácio C. Neto
2006	B	`conf`	A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. FPL Mário P. Véstias, Horácio C. Neto
2006	—	`conf`	Area and performance optimization of a generic network-on-chip architecture. SBCCI Mário P. Véstias, Horácio C. Neto
2006	—	`conf`	Area/Performance Improvement of NoC Architectures. ARC Mário P. Véstias, Horácio C. Neto
2006	—	`conf`	Co-synthesis of a configurable SoC platform based on a network on chip architecture. ASP-DAC Mário P. Véstias, Horácio C. Neto
2006	B	`conf`	On Reconfigurable Architectures for Efficient Matrix Inversion. FPL Goncalo M. de Matos, Horácio C. Neto
2005	B	`conf`	An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning. FPL Pedro M. Domingos, Fernando M. Silva, Horácio C. Neto
2005	—	`conf`	Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping. SAMOS Ricardo S. Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto
2004	B	`conf`	An Environment for Exploring Data-Driven Architectures. FPL Ricardo S. Ferreira, João M. P. Cardoso, Horácio C. Neto
2003	J	`jnl`	Compilation for FPGA-Based Reconfigurable Hardware. IEEE Des. Test Comput. João M. P. Cardoso, Horácio C. Neto
2003	—	`conf`	DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. SBCCI Mário P. Véstias, Horácio C. Neto
2002	C	`conf`	System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures. IEEE International Workshop on Rapid System Prototyping Mário P. Véstias, Horácio C. Neto
2001	J	`jnl`	An exact solution to the minimum size test pattern problem. ACM Trans. Design Autom. Electr. Syst. Paulo F. Flores, Horácio C. Neto, João P. Marques Silva
2001	B	`conf`	Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines. FPL João M. P. Cardoso, Horácio C. Neto
1999	—	`conf`	An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs. VLSI João M. P. Cardoso, Horácio C. Neto
1999	Misc	`conf`	Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. VLSI Design Paulo F. Flores, José C. Costa, Horácio C. Neto, José Monteiro, João Marques-Silva
1999	Misc	`conf`	Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System. FCCM João M. P. Cardoso, Horácio C. Neto
1999	—	`conf`	On Applying Set Covering Models to Test Set Compaction. Great Lakes Symposium on VLSI Paulo F. Flores, Horácio C. Neto, João P. Marques Silva
1999	—	`conf`	Test pattern generation for width compression in BIST. ISCAS (1) Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva
1998	C	`conf`	An exact solution to the minimum size test pattern problem. ICCD Paulo F. Flores, Horácio C. Neto, João P. Marques Silva
1998	—	`conf`	Towards an automatic path from Java ICECS João M. P. Cardoso, Horácio C. Neto
1994	Misc	`conf`	Bitwise Encoding of Finite State Machines. VLSI Design José Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto
1992	J	`jnl`	On exponential fitting for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Luís Miguel Silveira, Jacob K. White, Horácio C. Neto, Luís M. Vidigal