Hortensia Mecha

29 papers A 5B 1C 1Misc 1Journal 12Unranked 9
YearRankTypeTitle / Venue / Authors
2023 J jnl
SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles.
Microprocess. Microsystems
Juan Carlos Fabero, Golnaz Korkian, Francisco J. Franco, Guillaume Hubert, Hortensia Mecha, Manon Letiche, Juan Antonio Clemente
2022 J jnl
Single Event Upsets Under Proton, Thermal, and Fast Neutron Irradiation in Emerging Nonvolatile Memories.
IEEE Access
Golnaz Korkian, Daniel León, Francisco J. Franco, Juan Carlos Fabero, Manon Letiche, Yolanda Morilla, Pedro Martín-Holgado, Helmut Puchner, Hortensia Mecha, Juan Antonio Clemente
2021 — conf
Impact of DVS on Power Consumption and SEE Sensitivity of COTS Volatile SRAMs.
LATS
Mohammadreza Rezaei, Francisco J. Franco, Juan Carlos Fabero, Hortensia Mecha, Helmut Puchner, Juan Antonio Clemente
2021 — conf
Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident Angles.
LATS
Juan Carlos Fabero, Golnaz Korkian, Francisco J. Franco, Hortensia Mecha, Manon Letiche, Juan Antonio Clemente
2020 J jnl
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Adrián Alcolea Morena, Javier Olivito, Javier Resano, Hortensia Mecha
2018 J jnl
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.
IET Comput. Digit. Tech.
Javier Olivito, Felipe Serrano, Juan Antonio Clemente, Hortensia Mecha, Javier Resano
2016 J jnl
Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs.
Neurocomputing
Juan Antonio Clemente, Wassim Mansour, Rafic Ayoubi, Felipe Serrano, Hortensia Mecha, Haissam Ziade, Wassim El Falou, Raoul Velazco
2016 A conf
Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA.
DATE
Marcos Sánchez-Élez, Inmaculada Pardines, Felipe Serrano, Hortensia Mecha
2010 — conf
A Constant Complexity Allocation Algorithm for Reconfigurable Systems Management Adapted to Heterogeneous Workload Profiles.
ERSA
Sara Román Navarro, Hortensia Mecha, Daniel Mozos
2009 A conf
3D FPGA resource management and fragmentation metric for hardware multitasking.
IPDPS
Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha
2008 J jnl
Allocation heuristics and defragmentation measures for reconfigurable systems management.
Integr.
Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
2008 J jnl
Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays.
IET Comput. Digit. Tech.
S. Roman, Hortensia Mecha, Daniel Mozos, Julio Septién
2008 — conf
FPGA Resource Management Using Internal RAM as Aata Cache.
ERSA
Laura Sánchez, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo
2008 A conf
Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking.
IPDPS
Julio Septién, Daniel Mozos, Hortensia Mecha, Jesús Tabero, Miguel Angel García de Dios
2008 — conf
Resource Management for Hw Multitasking in Three Dimensional FPGAs.
ERSA
Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo
2008 — conf
Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system.
ERSA
Angel Luis González Bravo, Hortensia Mecha, Julio Septién, Sara Román Navarro, Daniel Mozos
2006 A conf
2D defragmentation heuristics for hardware multitasking on reconfigurable devices.
IPDPS
Julio Septién, Hortensia Mecha, Daniel Mozos, Jesús Tabero
2006 — conf
Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs.
ARC
Sara Román Navarro, Julio Septién, Hortensia Mecha, Daniel Mozos
2006 C conf
Partition Based Dynamic 2D HW Multitasking Management.
DSD
Sara Román Navarro, Hortensia Mecha, Daniel Mozos, Julio Septién
2006 — conf
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems.
ASP-DAC
Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
2004 B conf
A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management.
FPL
Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
2003 — conf
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements.
PATMOS
Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién
2003 J jnl
Analyzing communication overheads during hardware/software partitioning.
Microelectron. J.
Javier Resano, M. Elena Pérez, Daniel Mozos, Hortensia Mecha, Julio Septién
1999 J jnl
Unified data path allocation and BIST intrusion.
Integr.
Katzalin Olcoz, Francisco Tirado, Hortensia Mecha
1998 A conf
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process.
DATE
Juan Antonio Maestro, Daniel Mozos, Hortensia Mecha
1997 J jnl
A unified approach for scheduling and allocation.
Integr.
R. Moreno, Román Hermida, Milagros Fernández, Hortensia Mecha
1997 Misc conf
Interconnection Delay and Clock Cycle Selection in High Level Synthesis.
VLSI Design
Hortensia Mecha, Milagros Fernández
1996 J jnl
A method for area estimation of data-path in high level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hortensia Mecha, Milagros Fernández, Francisco Tirado, Julio Septién, D. Motes, Katzalin Olcoz
1994 J jnl
Clock cycle estimation based on dead time and control unit area minimization.
Microprocess. Microprogramming
Hortensia Mecha, Milagros Fernández, Román Hermida, Daniel Mozos, Katzalin Olcoz