Horst A. Gieser

16 papers A 2Journal 11Unranked 3
YearRankTypeTitle / Venue / Authors
2025 A conf
Multi-Partner Project: Reverse Engineering Methods for Trusted Chip Design (RESEC).
DATE
Bernhard Lippmann, Johanna Baehr, Alexander Hepp, Horst A. Gieser
2024 — conf
Analysis of Piezoresistive Silicon as Sense Element for use in Flexible Tactile Sensors.
IEEE SENSORS
Vartika Verma, Eslam Ahmed, Nicola Kovac, Christof Landesberger, Horst A. Gieser, Ralf Brederlow
2022 A conf
Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions.
DATE
Bernhard Lippmann, Ann-Christin Bette, Matthias Ludwig, Johannes Mutter, Johanna Baehr, Alexander Hepp, Horst A. Gieser, Nicola Kovac, Tobias Zweifel, Martin Rasche, Oliver Kellermann
2020 J jnl
Investigating Profiled Side-Channel Attacks Against the DES Key Schedule.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Johann Heyszl, Katja Miller, Florian Unterstein, Marc Schink, Alexander Wagner, Horst A. Gieser, Sven Freud, Tobias Damm, Dominik Klein, Dennis Kügler
2020 J jnl
Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies.
Integr.
Bernhard Lippmann, Niklas Unverricht, Aayush Singla, Matthias Ludwig, Michael Werner, Peter Egger, Anja Dübotzky, Helmut Gräb, Horst A. Gieser, Martin Rasche, Oliver Kellermann
2019 — conf
Integrated flow for reverse engineering of nanoscale technologies.
ASP-DAC
Bernhard Lippmann, Michael Werner, Niklas Unverricht, Aayush Singla, Peter Egger, Anja Dübotzky, Horst A. Gieser, Martin Rasche, Oliver Kellermann, Helmut Graeb
2019 J jnl
Investigating Profiled Side-Channel Attacks Against the DES Key Schedule.
IACR Cryptol. ePrint Arch.
Johann Heyszl, Katja Miller, Florian Unterstein, Marc Schink, Alexander Wagner, Horst A. Gieser, Sven Freud, Tobias Damm, Dominik Klein, Dennis Kügler
2015 — conf
Electrostatic discharge sensitivity investigation on organic field-effect thin film transistors.
NEWCAS
Tekfouy Lim, Horst A. Gieser, Luca Santarelli, Franco Cacialli
2009 J jnl
Investigating the CDM susceptibility of IC's at package and wafer level by capacitive coupled TLP.
Microelectron. Reliab.
Heinrich Wolf, Horst A. Gieser, Dirk Walter
2006 J jnl
ESD Susceptibility of Submicron Air Gaps.
Microelectron. Reliab.
Heinrich Wolf, Horst A. Gieser, Detlef Bonfert, Markus Hauser
2006 J jnl
Study of CDM specific effects for a smart power input protection structure.
Microelectron. Reliab.
M. Etherton, Ning Qu, J. Willemen, Wolfgang Wilkening, S. Mettler, Mariano Dissegna, R. Stella, L. Zullino, A. Andreini, Horst A. Gieser
2006 J jnl
Transient-induced latch-up test setup for wafer-level and package-level.
Microelectron. Reliab.
Detlef Bonfert, Horst A. Gieser, Heinrich Wolf, M. Frank, A. Konrad, J. Schulz
2005 J jnl
A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits.
Microelectron. Reliab.
Heinrich Wolf, Horst A. Gieser, Wolfgang Soldner, Harald Gossner
2005 J jnl
Capacitively coupled transmission line pulsing cc-TLP--a traceable and reproducible stress method in the CDM-domain.
Microelectron. Reliab.
Heinrich Wolf, Horst A. Gieser, Wolfgang Stadler, Wolfgang Wilkening
2005 J jnl
Transient latch-up: experimental analysis and device simulation.
Microelectron. Reliab.
S. Bargstädt-Franke, Wolfgang Stadler, Kai Esmark, Martin Streibl, Krzysztof Domanski, Horst A. Gieser, Heinrich Wolf, Waclaw Bala
2003 J jnl
On-chip electrostatic discharge ESD.
Microelectron. Reliab.
Horst A. Gieser