Hormoz Djahanshahi

21 papers C 2Journal 8Unranked 11
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20-28GHz LCVCO and a 51-62GHz Self-Mixing LCVCO.
IEEE Trans. Circuits Syst. I Regul. Pap.
Omid Esmaeeli, Sam Lightbody, Amir Hossein Masnadi Shirazi, Hormoz Djahanshahi, Rod Zavari, Shahriar Mirabbasi, Sudip Shekhar
2020 — conf
A Compact Dual-Core 26.1-to-29.9GHz Coupled-CMOS LC-VCO with Implicit Common-Mode Resonance and FoM of-191 dBc/Hz at 10MHz.
CICC
Amir Hossein Masnadi Shirazi, Mohammad Mahani, Hossein Miri Lavasani, Shahriar Mirabbasi, Sudip Shekhar, Rod Zavari, Hormoz Djahanshahi
2018 — conf
A Hardened-By-Design Technique for LC-Tank Voltage Controlled Oscillator.
CCECE
Zhichao Zhang, Li Chen, Hormoz Djahanshahi
2018 — conf
A SEE Insensitive CML Voltage Controlled Oscillator in 65nm CMOS.
CCECE
Zhichao Zhang, Li Chen, Hormoz Djahanshahi
2018 C conf
On the Design of Vertical-Turn Solenoids for Magnetically Isolated Densely Integrated LC Oscillators.
ISCAS
Milad Haghi Kashani, Reza Molavi, Hormoz Djahanshahi, Shahriar Mirabbasi
2016 J jnl
On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise.
IEEE J. Solid State Circuits
Amir Hossein Masnadi Shirazi, Amir Nikpaik, Reza Molavi, Sam Lightbody, Hormoz Djahanshahi, Mazhareddin Taghivand, Shahriar Mirabbasi, Sudip Shekhar
2013 J jnl
Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration.
J. Electr. Comput. Eng.
Reza Molavi, Hormoz Djahanshahi, Rod Zavari, Shahriar Mirabbasi
2012 — conf
Design and verification of integrated inductors in CMOS.
CCECE
Reza Molavi, Shahriar Mirabbasi, Hormoz Djahanshahi
2011 C conf
A 27-GHz low-power push-push LC VCO with wide tuning range in 65nm CMOS.
ISCAS
Reza Molavi, Shahriar Mirabbasi, Hormoz Djahanshahi
2006 J jnl
Modeling and Characterization of VCOs with MOS Varactors for RF Transceivers.
EURASIP J. Wirel. Commun. Netw.
Pedram Sameni, Chris Siu, Shahriar Mirabbasi, Hormoz Djahanshahi, Marwa Hamour, Krzysztof Iniewski, Jatinder Chana
2005 — conf
Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO.
ISCAS (5)
Pedram Sameni, Chris Siu, Shahriar Mirabbasi, Hormoz Djahanshahi, Marwa Hamour, Krzysztof Iniewski, Jatinder Chana
2000 J jnl
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications.
IEEE J. Solid State Circuits
Hormoz Djahanshahi, C. André T. Salama
1999 — conf
Differential 0.35µm CMOS circuits for 622 MHz/933 MHz monolithic clock and data recovery applications.
ISCAS (2)
Hormoz Djahanshahi, C. André T. Salama
1999 — conf
Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling.
CICC
Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama
1999 J jnl
Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS.
IEEE J. Solid State Circuits
Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama
1999 — conf
Sensitivity study and improvements on a nonlinear resistive-type neuron circuit.
ICECS
Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller
1998 J jnl
A Low-Variation Nonlinear Neuron Circuit.
J. Circuits Syst. Comput.
Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller
1998 — conf
High-speed ECL-compatible serial I/O in 0.35 μm CMOS.
ICECS
Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama
1998 J jnl
Neural Network Integrated Circuits with Single-Block Mixed Signal Arrays.
J. Circuits Syst. Comput.
Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller
1996 — conf
A modular architecture for hybrid VLSI neural networks and its application in a smart photosensor.
ICNN
Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller
1996 — conf
Design and VLSI Implementation of a Unified Synapse-Neuron Architecture.
Great Lakes Symposium on VLSI
Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller