Hoonki Kim - RankMe

12 papers Journal 6Unranked 6

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10-nm SRAM Designs. IEEE Trans. Circuits Syst. II Express Briefs Tae-Hyun Kim, Juhyun Park, In Jun Jung, Hoonki Kim, Taejoong Song, Seong-Ook Jung
2023	—	`conf`	Breakthrough Design Technology Co-optimization using BSPDN and Standard Cell Variants for Maximizing Block-level PPA. VLSI Technology and Circuits Seungyoung Lee, Sungyup Jung, Yunkyeong Jang, Jungho Do, Jisu Yu, Hyeoungyu You, Minjae Jeong, Jinyoung Lim, Jiyun Han, Sangdo Park, Yongdeok Kim, Jooyeon Kwon, Hoonki Kim, Seiseung Yoon
2022	—	`conf`	3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology. CICC Taejoong Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang, Hayoung Kim, Dongwook Seo, Hoonki Kim, Woojin Rim, Sanghoon Baek, Sangyeop Baeck, Jonghoon Jung
2022	J	`jnl`	A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit. IEEE J. Solid State Circuits Taejoong Song, Hoonki Kim, Woojin Rim, Hakchul Jung, Changnam Park, Inhak Lee, Sanghoon Baek, Jonghoon Jung
2021	—	`conf`	24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit. ISSCC Taejoong Song, Woojin Rim, Hoonki Kim, Keun Hwi Cho, Taeyeong Kim, Taejung Lee, Geumjong Bae, Dong-Won Kim, S. D. Kwon, Sanghoon Baek, Jonghoon Jung, Jongwook Kye, Hakchul Jung, HyungTae Kim, Soon-Moon Jung, Jaehong Park
2021	J	`jnl`	A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. IEEE J. Solid State Circuits Hanwool Jeong, Tae Hyun Kim, Changnam Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung
2020	J	`jnl`	An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache. IEEE Access Tae Hyun Kim, Hanwool Jeong, Juhyun Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung
2019	J	`jnl`	Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving. IEEE J. Solid State Circuits Hanwool Jeong, Se Hyeok Oh, Tae Woo Oh, Hoonki Kim, Changnam Park, Woojin Rim, Taejoong Song, Seong-Ook Jung
2018	—	`conf`	A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. ISSCC Taejoong Song, Jonghoon Jung, Woojin Rim, Hoonki Kim, Yongho Kim, Changnam Park, Jeongho Do, Sunghyun Park, Sungwee Cho, Hyuntaek Jung, Bongjae Kwon, Hyun-Su Choi, Jaeseung Choi, Jong Shik Yoon
2018	—	`conf`	Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. VLSI Circuits Woong Choi, Jongsun Park, Hoonki Kim, Changnam Park, Taejoong Song
2017	—	`conf`	12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. ISSCC Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi
2017	J	`jnl`	A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization. IEEE J. Solid State Circuits Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Giyong Yang, Hoonki Kim, Sanghoon Baek, Jonghoon Jung, Bongjae Kwon, Sungwee Cho, Hyuntaek Jung, Yongjae Choo, Jaeseung Choi