Hongzhuo Liu - RankMe

14 papers Journal 6Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Cycle-Slip Compensated FMCW Digital PLL With Background Back-Tracking DPD. IEEE J. Solid State Circuits Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Zhihua Wang, Baoyong Chi
2025	—	`conf`	A 0.18-µs-Locking-Time Fractional-N PLL with Stochastic Gradient Descent Tuning Curve Fitting, Initial Phase Error Zeroing, and Random DSM Achieving 44.4-fs Jitter at Near-Integer Channel. CICC Hongzhuo Liu, Wei Deng, Haikun Jia, Baoyong Chi
2025	J	`jnl`	A Series-Parallel-Resonance Oscillator With a 191.5 dBc/Hz FoM. IEEE Solid State Circuits Lett. Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Junlong Gong, Qiuyu Peng, Baoyong Chi
2025	J	`jnl`	A Transformer-Based Series-Resonance CMOS VCO. IEEE J. Solid State Circuits Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Zhihua Wang, Baoyong Chi
2025	J	`jnl`	An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths. IEEE J. Solid State Circuits Hongzhuo Liu, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi
2024	J	`jnl`	A Multireference PLL: Theory and Implementation. IEEE J. Solid State Circuits Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Zhihua Wang, Baoyong Chi
2024	—	`conf`	An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter. CICC Hongzhuo Liu, Wei Deng, Haikun Jia, Baoyong Chi
2024	J	`jnl`	An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique. IEEE J. Solid State Circuits Qixiu Wu, Wei Deng, Yaqian Sun, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi
2023	—	`conf`	A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS. CICC Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi
2023	—	`conf`	A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter. ESSCIRC Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Baoyong Chi
2023	—	`conf`	An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. VLSI Technology and Circuits Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi
2023	—	`conf`	An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique. ISSCC Qixiu Wu, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi
2023	—	`conf`	IEEE ASSCC 2023/ Session 10/ Paper 10.5. A-SSCC Ruichang Ma, Haikun Jia, Hongzhuo Liu, Wei Deng, Zhihua Wang, Baoyong Chi
2022	—	`conf`	A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logN ESSCIRC Hongzhuo Liu, Wei Deng, Haikun Jia, Shiyan Sun, Qixiu Wu, Jiajie Tang, Zhihua Wang, Baoyong Chi