Hongyu Chen - RankMe

22 papers A* 2A 2C 3Journal 4Unranked 11

Year	Rank	Type	Title / Venue / Authors
2011	J	`jnl`	On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals. IEEE Trans. Very Large Scale Integr. Syst. Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng
2007	—	`conf`	Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. ASP-DAC Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen
2007	J	`jnl`	Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng
2007	—	`conf`	Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. ISQED Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng
2006	A*	`conf`	Communication latency aware low power NoC synthesis. DAC Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng
2006	—	`conf`	Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. ASP-DAC Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton
2005	—	`conf`	A multi-level transmission line network approach for multi-giga hertz clock distribution. ASP-DAC Hongyu Chen, Chung-Kuan Cheng
2005	A	`conf`	Improving the efficiency of static timing analysis with false paths. ICCAD Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
2005	C	`conf`	Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz. ICCD Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng
2005	C	`conf`	Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications. ICCD Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris
2005	J	`jnl`	The Y architecture for on-chip interconnect: analysis and methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
2005	—	`conf`	Unified quadratic programming approach for mixed mode placement. ISPD Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris
2004	—	`conf`	A multiple level network approach for clock skew minimization with process variations. ASP-DAC Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng
2004	—	`conf`	Optimal planning for mesh-based power distribution. ASP-DAC Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang
2003	A*	`conf`	An algebraic multigrid solver for analytical placement with layout based clustering. DAC Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
2003	—	`conf`	Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. SLIP Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang
2003	J	`jnl`	Floorplan representations: Complexity and connections. ACM Trans. Design Autom. Electr. Syst. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham
2003	A	`conf`	The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. ICCAD Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
2003	—	`conf`	The Y-architecture: yet another on-chip interconnect solution. ASP-DAC Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
2002	C	`conf`	Physical Planning Of On-Chip Interconnect Architectures. ICCD Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
2002	—	`conf`	Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. SLIP Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng
2001	—	`conf`	Revisiting floorplan representations. ISPD Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham