Hongwu Jiang

35 papers A* 2A 4C 2Journal 15Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
Voxel-PIM: An Efficient Process-in-Memory Based ASIC Accelerator for Voxel-Based Point Cloud Neural Networks.
IEEE Trans. Computers
Xipeng Lin, Shaoxuan Li, Shanshi Huang, Hongwu Jiang
2025 A* conf
An Efficient Compute-in-Memory based Accelerator for Point-based Point Cloud Neural Networks.
DAC
Xipeng Lin, Cong Wang, Shanshi Huang, Hongwu Jiang
2025 A conf
OpenC
DATE
Tianchu Dong, Shaoxuan Li, Yihang Zuo, Hongwu Jiang, Yuzhe Ma, Shanshi Huang
2024 A conf
Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural Networks.
ICCAD
Xipeng Lin, Shanshi Huang, Hongwu Jiang
2024 J jnl
Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural Networks.
CoRR
Xipeng Lin, Shanshi Huang, Hongwu Jiang
2023 — —
Architecture and Circuit Design Optimization for Compute-In-Memory.
Hongwu Jiang
2023 J jnl
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hongwu Jiang, Shanshi Huang, Wantong Li, Shimeng Yu
2023 J jnl
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators.
ACM Trans. Design Autom. Electr. Syst.
Shanshi Huang, Hongwu Jiang, Shimeng Yu
2022 J jnl
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References.
IEEE J. Solid State Circuits
Wantong Li, Xiaoyu Sun, Shanshi Huang, Hongwu Jiang, Shimeng Yu
2022 — conf
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays.
VLSI Technology and Circuits
Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu
2022 — conf
A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling.
ESSCIRC
Wantong Li, James Read, Hongwu Jiang, Shimeng Yu
2022 J jnl
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices.
ACM Trans. Design Autom. Electr. Syst.
Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
2022 J jnl
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators.
IEEE Des. Test
Hongwu Jiang, Wantong Li, Shanshi Huang, Stefan Cosemans, Francky Catthoor, Shimeng Yu
2022 J jnl
MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Wantong Li, James Read, Hongwu Jiang, Shimeng Yu
2022 J jnl
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.
IEEE J. Solid State Circuits
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang
2021 — conf
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References.
ESSCIRC
Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu
2021 — conf
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References.
ESSDERC
Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu
2021 J jnl
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
2021 C conf
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning.
ISCAS
Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu
2021 — conf
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune.
NVMSA
Shanshi Huang, Hongwu Jiang, Shimeng Yu
2021 J jnl
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune.
CoRR
Shanshi Huang, Hongwu Jiang, Shimeng Yu
2021 J jnl
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.
Frontiers Artif. Intell.
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2021 — conf
NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro.
AICAS
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2021 J jnl
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption.
IEEE Trans. Very Large Scale Integr. Syst.
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
2021 — conf
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security.
CICC
Wantong Li, Shanshi Huang, Xiaoyu Sun, Hongwu Jiang, Shimeng Yu
2020 — conf
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
ISSCC
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang
2020 — conf
8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator.
MWSCAS
Hongwu Jiang, Rui Liu, Shimeng Yu
2020 A* conf
A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.
DAC
Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu
2020 — conf
Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine.
MEMSYS
Wonbo Shim, Hongwu Jiang, Xiaochen Peng, Shimeng Yu
2020 J jnl
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays.
IEEE Trans. Computers
Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
2020 J jnl
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training.
CoRR
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
2020 C conf
MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture.
ISCAS
Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu
2020 A conf
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories.
DATE
Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
2020 A conf
XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption.
ICCAD
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
2019 — conf
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training.
MEMSYS
Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu