Hongce Zhang - RankMe

48 papers A* 7A 7B 4C 1Journal 21Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking. CoRR Guangyu Hu, Chen Chen, Xiaofeng Zhou, Jiaxi Zhang, Wei Zhang, Hongce Zhang
2026	A*	`conf`	BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning. AAAI Mingkai Miao, Jianheng Tang, Guangyu Hu, Hongce Zhang
2026	—	`conf`	EvolveGen : Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning. TACAS (2) Guangyu Hu, Xiaofeng Zhou, Wei Zhang, Hongce Zhang
2026	J	`jnl`	EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning. CoRR Guangyu Hu, Xiaofeng Zhou, Wei Zhang, Hongce Zhang
2026	J	`jnl`	LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking. CoRR Mingkai Miao, Guangyu Hu, Wei Zhang, Hongce Zhang
2026	—	`conf`	ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multipliers. TACAS (2) Chen Chen, Daniela Kaufmann, Chenhui Deng, Zhan Song, Hongce Zhang, Cunxi Yu
2025	—	`conf`	A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. ASP-DAC Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2025	—	`conf`	AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. ASP-DAC Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang
2025	J	`jnl`	BDD2Seq: Enabling Scalable Reversible-Circuit Synthesis via Graph-to-Sequence Learning. CoRR Mingkai Miao, Jianheng Tang, Guangyu Hu, Hongce Zhang
2025	A*	`conf`	E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis. DAC Chen Chen, Guangyu Hu, Cunxi Yu, Yuzhe Ma, Hongce Zhang
2025	J	`jnl`	E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis. CoRR Chen Chen, Guangyu Hu, Cunxi Yu, Yuzhe Ma, Hongce Zhang
2025	J	`jnl`	Functional Reduction to Speed Up Bounded Model Checking. CoRR Changyuan Yu, Wenbin Che, Hongce Zhang
2025	C	`conf`	Hot-FV: A Semi-Formal Test Generation Framework for RTL Functional Coverage Using Warm Starting States. ICCD Ziyue Zheng, Zhiyuan Yan, Xiangchen Meng, Guangyu Hu, Hongce Zhang, Yangdi Lyu
2025	A*	`conf`	NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. DAC Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie
2025	J	`jnl`	NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. CoRR Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie
2025	J	`jnl`	RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie
2025	J	`jnl`	ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multipliers. CoRR Chen Chen, Daniela Kaufmann, Chenhui Deng, Zhan Song, Hongce Zhang, Cunxi Yu
2025	J	`jnl`	SMT-Sweep: Word-Level Representation Unification for Hardware Verification. CoRR Ziyi Yang, Guangyu Hu, Mingkai Miao, Changyuan Yu, Hongce Zhang
2025	J	`jnl`	Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2025	A	`conf`	Word-Level Counterexample Reduction Methods for Hardware Verification. DATE Zhiyuan Yan, Hongce Zhang
2024	A*	`conf`	Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. DAC Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2024	J	`jnl`	Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. CoRR Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2024	J	`jnl`	AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang
2024	J	`jnl`	AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, Zhiyao Xie
2024	A	`conf`	AsymSAT: Accelerating SAT Solving with Asymmetric Graph-Based Model Prediction. DATE Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang
2024	B	`conf`	DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction. ASPDAC Guangyu Hu, Jianheng Tang, Changyuan Yu, Wei Zhang, Hongce Zhang
2024	A*	`conf`	E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis. DAC Chen Chen, Guangyu Hu, Dongsheng Zuo, Cunxi Yu, Yuzhe Ma, Hongce Zhang
2024	J	`jnl`	E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis. CoRR Chen Chen, Guangyu Hu, Dongsheng Zuo, Cunxi Yu, Yuzhe Ma, Hongce Zhang
2024	A	`conf`	Word-Level Augmentation of Formal Proof by Learning from Simulation Traces. ICCAD Zhiyuan Yan, Hongce Zhang
2023	J	`jnl`	Addressing Variable Dependency in GNN-based SAT Solving. CoRR Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang
2023	A*	`conf`	INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms. DAC Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik
2023	A	`conf`	MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. ICCAD Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2023	J	`jnl`	MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. CoRR Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2023	—	`conf`	NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model Checking. MLCAD Guangyu Hu, Wei Zhang, Hongce Zhang
2023	J	`jnl`	RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. CoRR Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie
2023	—	`conf`	WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification. TACAS (2) Wenji Fang, Hongce Zhang
2023	J	`jnl`	r-map: Relating Implementation and Specification in Hardware Refinement Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wenji Fang, Guangyu Hu, Hongce Zhang
2021	A	`conf`	Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. ICCAD Yu Zeng, Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik
2021	—	`conf`	Pono: A Flexible and Extensible SMT-Based Model Checker. CAV (2) Makai Mann, Ahmed Irfan, Florian Lonsing, Yahan Yang, Hongce Zhang, Kristopher Brown, Aarti Gupta, Clark W. Barrett
2021	B	`conf`	Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking. VMCAI Hongce Zhang, Aarti Gupta, Sharad Malik
2020	A*	`conf`	In Search for a SAT-friendly Binarized Neural Network Architecture. ICLR Nina Narodytska, Hongce Zhang, Aarti Gupta, Toby Walsh
2020	B	`conf`	Synthesizing Environment Invariants for Modular Hardware Verification. VMCAI Hongce Zhang, Weikun Yang, Grigory Fedyukovich, Aarti Gupta, Sharad Malik
2020	A	`conf`	Verification of Recurrent Neural Networks for Cognitive Tasks via Reachability Analysis. ECAI Hongce Zhang, Maxwell Shinn, Aarti Gupta, Arie Gurfinkel, Nham Le, Nina Narodytska
2019	—	`conf`	ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions. TACAS (1) Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik
2019	J	`jnl`	Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. ACM Trans. Design Autom. Electr. Syst. Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik
2018	B	`conf`	ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification. FMCAD Hongce Zhang, Caroline Trippel, Yatin A. Manerkar, Aarti Gupta, Margaret Martonosi, Sharad Malik
2018	J	`jnl`	Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. CoRR Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik
2016	A	`conf`	A hardware-based technique for efficient implicit information flow tracking. ICCAD Jangseop Shin, Hongce Zhang, Jinyong Lee, Ingoo Heo, Yu-Yuan Chen, Ruby B. Lee, Yunheung Paek