Hong Wang - RankMe

42 papers A* 19A 6B 3C 1Journal 6Unranked 7

Year	Rank	Type	Title / Venue / Authors
2019	A	`conf`	Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power. DATE Dipan Kumar Mandal, Srivatsava Jandhyala, Om Ji Omer, Gurpreet S. Kalsi, Biji George, Gopi Neela, Santhosh Kumar Rethinagiri, Sreenivas Subramoney, Lance Hacking, Jim Radford, Eagle Jones, Belliappa Kuttanna, Hong Wang
2018	A*	`conf`	Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. DAC Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney, Tanay Karnik, Hong Wang
2018	A*	`conf`	Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies. ISCA Anant Nori, Jayesh Gaur, Siddharth Rai, Sreenivas Subramoney, Hong Wang
2018	A*	`conf`	Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. ISCA Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, Hong Wang
2018	J	`jnl`	MARS: Memory Aware Reordered Source. CoRR Ishwar Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, Hong Wang
2018	—	`conf`	Tackling memory access latency through DRAM row management. MEMSYS Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang
2011	—	`conf`	AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs. Conf. Computing Frontiers Guilherme Ottoni, Gautham N. Chinya, Gerolf Hoflehner, Jamison D. Collins, Amit Kumar, Ethan Schuchman, David R. Ditzel, Ronak Singhal, Hong Wang
2011	J	`jnl`	Bothnia: a dual-personality extension to the Intel integrated graphics driver. ACM SIGOPS Oper. Syst. Rev. Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Hong Jiang, Guei-Yuan Lueh, Thomas Piazza, Hong Wang
2011	—	`conf`	Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture. Conf. Computing Frontiers Guilherme Ottoni, Thomas Hartin, Christopher T. Weaver, Jason Brandt, Belliappa Kuttanna, Hong Wang
2010	A*	`conf`	BLoG: post-silicon bug localization in processors using bug localization graphs. DAC Sung-Boem Park, Anne Bracy, Hong Wang, Subhasish Mitra
2010	A	`conf`	Intel nehalem processor core made FPGA synthesizable. FPGA Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang
2009	A*	`conf`	Criticality-based optimizations for efficient load processing. HPCA Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh
2009	A	`conf`	Intel® atom FPGA Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang
2008	A*	`conf`	CPR: Composable performance regression for scalable multiprocessor models. MICRO Benjamin C. Lee, Jamison D. Collins, Hong Wang, David M. Brooks
2008	A*	`conf`	Merge: a programming model for heterogeneous multi-core systems. ASPLOS Michael D. Linderman, Jamison D. Collins, Hong Wang, Teresa H. Meng
2008	J	`jnl`	Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. IEEE Trans. Parallel Distributed Syst. Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, John Paul Shen
2008	B	`conf`	Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. PACT Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang
2008	B	`conf`	Processor Performance Modeling using Symbolic Simulation. ISPASS Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang, Mark Horowitz
2007	A*	`conf`	EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. PLDI Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang
2007	A	`conf`	Sequencer virtualization. ICS Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang
2006	A*	`conf`	Multiple Instruction Stream Processor. ISCA Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan N. Rakvic, Hong Wang, John Paul Shen
2005	A	`conf`	A Dependency Chain Clustered Microarchitecture. IPDPS Satish Narayanasamy, Hong Wang, Perry H. Wang, John Paul Shen, Brad Calder
2004	C	`conf`	Best of Both Latency and Throughput. ICCD Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang
2004	A*	`conf`	Control Flow Optimization Via Dynamic Reconvergence Prediction. MICRO Jamison D. Collins, Dean M. Tullsen, Hong Wang
2004	A*	`conf`	Hardware Support for Prescient Instruction Prefetch. HPCA Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen
2004	J	`jnl`	Helper Threads via Virtual Multithreading. IEEE Micro Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
2004	A*	`conf`	Helper threads via virtual multithreading on an experimental itanium ASPLOS Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
2004	A	`conf`	Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. CGO Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar, John Paul Shen
2003	A*	`conf`	A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen
2003	B	`conf`	Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations. ISPASS Hong Wang, Shiri Manor, Dave LaFollette, Nadav Nesher, Ku-Jei King, Perry H. Wang, Shay Levy, Shai Satt, Gal Carmeli, Arjun Kapur, Ioannis Schoinas, Ed Rubinstein, Rahul Bhatt
2002	A*	`conf`	Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. HPCA Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen
2002	A*	`conf`	Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. PLDI Shih-Wei Liao, Perry H. Wang, Hong Wang, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery
2002	—	`conf`	Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. Interaction between Compilers and Computer Architectures R. David Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen
2001	A*	`conf`	Dynamic speculative precomputation. MICRO Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen
2001	A*	`conf`	Register Renaming and Scheduling for Dynamic Execution of Predicated Code. HPCA Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen
2001	A*	`conf`	Speculative precomputation: long-range prefetching of delinquent loads. ISCA Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen
2000	—	`conf`	Redundant Arithmetic Optimizations (Research Note). Euro-Par Thomas Y. Yeh, Hong Wang
1997	J	`jnl`	Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags. IEEE Trans. Computers Hong Wang, Tong Sun, Qing Yang
1995	A*	`conf`	CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches. ISCA Hong Wang, Tong Sun, Qing Yang
1993	J	`jnl`	A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors. IEEE Trans. Parallel Distributed Syst. Qing Yang, Hong Wang
1992	—	`conf`	On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers. ICPP (1) Qing Yang, Hong Wang
1991	—	`conf`	Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors. ICPP (1) Hong Wang, Qing Yang