Hong-Yi Huang - RankMe

84 papers C 28Journal 28Unranked 28

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A traffic classification-based traffic engineering framework in software-defined networking. Int. J. Commun. Networks Distributed Syst. Chih-Yu Lin, Chien-Cheng Wu, Hong-Yi Huang
2025	—	`conf`	A 20 Gb/s Half-Rate PAM-4 Clock and Data Recovery with Data Independent Phase Tracking Compensation Technique. ICECS Kuang-Ya Wu, Kuo-Hsing Cheng, Yu-Yen Ke, Chih-Wei Tsai, Hong-Yi Huang
2025	—	`conf`	A 5 Gb/s Half-Rate Clock and Data Recovery with Adaptive Equalizer Using ISI Detecting Technique. ICECS Yan-Ci Li, Kuo-Hsing Cheng, Shi-Yang Sun, Hong-Yi Huang
2025	J	`jnl`	Quaff: Quantized Parameter-Efficient Fine-Tuning under Outlier Spatial Stability Hypothesis. CoRR Hong-Yi Huang, Dapeng Wu
2023	J	`jnl`	A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique. Circuits Syst. Signal Process. Hong-Yi Huang, Jen-Chieh Liu, Fu-Chien Tsai, Kun-Hua Lee, Kun-Yuan Chen
2023	—	`conf`	A 1~50mA 20ns Settling Time Low Dropout Regulator. ICECS Hong-Yi Huang, Yu-Ming Tsao, Angelo Nico M. Daroy, Kuo-Hsing Cheng
2023	—	`conf`	A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System. ICECS Kuo-Hsing Cheng, Chun-Yao Chang, Hong-Yi Huang, Yun-Teng Shih
2023	—	`conf`	A Prompt Engineering Approach to Scientific Text Simplification: CYUT at SimpleText2023 Task3. CLEF (Working Notes) Shih-Hung Wu, Hong-Yi Huang
2023	—	`conf`	Buck Converter with Variable Output Voltage for Dynamic Voltage Scaling (DVS) Applications. ISCIT Harreez M. Villaruz, Hong-Yi Huang, Nieva M. Mapula, Gene Fe P. Palencia
2023	—	`conf`	RF Energy Harvesting with Wide Input Power Range. ICECS Hong-Yi Huang, Chun-Wei Wu, Nieva M. Mapula
2023	—	`conf`	SimpleText Best of Labs in CLEF-2022: Simplify Text Generation with Prompt Engineering. CLEF Shih-Hung Wu, Hong-Yi Huang
2022	—	`conf`	CYUT Team2 SimpleText Shared Task Report in CLEF-2022. CLEF (Working Notes) Shih-Hung Wu, Hong-Yi Huang
2017	J	`jnl`	A 2.5 mW/ch, 50 Mcps, 10-Analog Channel, Adaptively Biased Read-Out Front-End IC With Low Intrinsic Timing Resolution for Single-Photon Time-of-Flight PET Applications With Time-Dependent Noise Analysis in 90 nm CMOS. IEEE Trans. Biomed. Circuits Syst. Hugo Cruz, Hong-Yi Huang, Ching-Hsing Luo, Shuenn-Yuh Lee
2017	C	`conf`	A novel clock-pulse-width calibration technique for charge redistribution DACs. ISCAS Hugo Cruz, Hong-Yi Huang, Ching-Hsing Luo, Lih-Yih Chiou, Shuenn-Yuh Lee
2016	J	`jnl`	A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. IEICE Electron. Express Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu
2016	J	`jnl`	A Distortion Cancelation Technique With the Recursive DFT Method for Successive Approximation Analog-to-Digital Converters. IEEE Trans. Circuits Syst. II Express Briefs Yi-Hsiang Juan, Hong-Yi Huang, Shin-Chi Lai, Wen-Ho Juang, Shuenn-Yuh Lee, Ching-Hsing Luo
2016	C	`conf`	A chaotically injected timing technique for ring-based oscillators. DDECS Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang
2016	C	`conf`	Gm-C filter with automatic calibration scheme. DDECS Hong-Yi Huang, Kun-Yuan Chen, Jia-Hao Xie, Ming-Ta Lee, Hao-Chiao Hong, Kuo-Hsing Cheng
2016	C	`conf`	Low-voltage indoor energy harvesting using photovoltaic cell. DDECS Hong-Yi Huang, Shao-Zu Yen, Jhen-Hong Chen, Hao-Chiao Hong, Kuo-Hsing Cheng
2015	J	`jnl`	A 1.3 mW low-IF, current-reuse, and current-bleeding RF front-end for the MICS band with sensitivity of -97 dbm. IEEE Trans. Circuits Syst. I Regul. Pap. Hugo Cruz, Hong-Yi Huang, Shuenn-Yuh Lee, Ching-Hsing Luo
2015	—	`conf`	A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS. VLSI-DAT Hugo Cruz, Hong-Yi Huang, Shueen-Yu Lee, Ching-Hsing Luo
2015	C	`conf`	A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. DDECS Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang
2015	C	`conf`	PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing. DDECS Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching-Hsing Luo, Jin-Chern Chiou
2015	C	`conf`	Triangular Modulation Using Switched-Capacitor Scheme for Spread-Spectrum Clocking. DDECS Hong-Yi Huang, Gene Fe P. Palencia, Da-Kai Chen, Wei-Hsuan Huang
2014	C	`conf`	A 64-MHz∼640-MHz 64-phase clock generator. DDECS Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng
2014	C	`conf`	A low supply voltage synchronous mirror delay with quadrature phase output. DDECS Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang
2014	C	`conf`	A radio-controlled receiver for clocks/watches and alarm applications. ISCAS Jen-Chieh Liu, Huan-Ke Chiu, Jia-Hung Peng, Yuan-Hua Chu, Hong-Yi Huang
2014	C	`conf`	Analysis and design of a 1.3-mW current-reuse RF front-end for the MICS band. ISCAS Hugo Cruz, Hong-Yi Huang, Shuenn-Yuh Lee, Ching-Hsing Luo
2013	J	`jnl`	A Low-Power Bio-Potential Acquisition System with Flexible PDMS Dry Electrodes for Portable Ubiquitous Healthcare Applications. Sensors Chih-Yuan Chen, Chia-Lin Chang, Chih-Wei Chang, Shin-Chi Lai, Tsung-Fu Chien, Hong-Yi Huang, Jin-Chern Chiou, Ching-Hsing Luo
2013	C	`conf`	A low jitter delay-locked-loop applied for DDR4. DDECS Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang
2013	J	`jnl`	Adaptive successive approximation ADC for biomedical acquisition system. Microelectron. J. Hui-Wen Chang, Hong-Yi Huang, Yi-Hsiang Juan, Wei-Song Wang, Ching-Hsing Luo
2013	C	`conf`	External capacitorless low dropout linear regulator using cascode structure. DDECS Hong-Yi Huang, Cheng-Yu Chen, Kuo-Hsing Cheng
2013	C	`conf`	Indoor energy harvesting using photovoltaic cell for battery recharging. DDECS Hong-Yi Huang, Chinet Otic Mocorro, Julyver Pinaso, Kuo-Hsing Cheng
2012	J	`jnl`	A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. IEEE Trans. Circuits Syst. II Express Briefs Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang
2012	—	`conf`	A low power analog front-end (AFE) circuit dedicated for driving bio-electrochemical sensors and peripheral devices. BioCAS Wei-Jhe Ma, Ching-Hsing Luo, Hong-Yi Huang
2012	C	`conf`	A low voltage sigma delta modulator for temperature sensor. DDECS Yi-Hsiang Juan, Ching-Hsing Luo, Hong-Yi Huang
2012	J	`jnl`	An Efficient Micro Control Unit with a Reconfigurable Filter Design for Wireless Body Sensor Networks (WBSNs). Sensors Chiung-An Chen, Shih-Lun Chen, Hong-Yi Huang, Ching-Hsing Luo
2012	J	`jnl`	An MICS band frequency synthesizer using active inductor and auto-calibration scheme. Microelectron. J. Hong-Yi Huang, Chun-Chieh Wu, Ching-Hsing Luo
2012	J	`jnl`	CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes. IEICE Trans. Electron. Hong-Yi Huang, Shiun-Dian Jan, Yang Chou, Cheng-Yu Chen
2011	J	`jnl`	A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. IEEE Trans. Circuits Syst. II Express Briefs Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu
2011	J	`jnl`	A Low-Cost High-Quality Adaptive Scalar for Real-Time Multimedia Applications. IEEE Trans. Circuits Syst. Video Technol. Shih-Lun Chen, Hong-Yi Huang, Ching-Hsing Luo
2011	C	`conf`	All digital phase-locked loop using active inductor oscillator and novel locking algorithm. ISCAS Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo
2011	J	`jnl`	An Asynchronous Multi-Sensor Micro Control Unit for Wireless Body Sensor Networks (WBSNs). Sensors Chiung-An Chen, Shih-Lun Chen, Hong-Yi Huang, Ching-Hsing Luo
2011	J	`jnl`	Differential bidirectional transceiver for on-chip long wires. Microelectron. J. Hong-Yi Huang, Ruei-Iun Pu
2011	J	`jnl`	Real-Time Telemetry System for Amperometric and Potentiometric Electrochemical Sensors. Sensors Wei-Song Wang, Hong-Yi Huang, Shu-Chun Chen, Kuo-Chuan Ho, Chia-Yu Lin, Tse-Chuan Chou, Chih-Hsien Hu, Wen-Fong Wang, Cheng-Feng Wu, Ching-Hsing Luo
2011	J	`jnl`	Time Multiplexed VLSI Architecture for Real-Time Barrel Distortion Correction in Video-Endoscopic Images. IEEE Trans. Circuits Syst. Video Technol. Shih-Lun Chen, Hong-Yi Huang, Ching-Hsing Luo
2010	J	`jnl`	A Power-Efficient Bio-Potential Acquisition Device with DS-MDE Sensors for Long-Term Healthcare Monitoring Applications. Sensors Chia-Lin Chang, Chih-Wei Chang, Hong-Yi Huang, Chen-Ming Hsu, Chia-Hsuan Huang, Jin-Chern Chiou, Ching-Hsing Luo
2010	C	`conf`	A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. DDECS Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang
2010	J	`jnl`	Variable-Latency Floating-Point Multipliers for Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. Shiann-Rong Kuang, Jiun-Ping Wang, Hong-Yi Huang
2010	J	`jnl`	Wide Dynamic Range CMOS Potentiostat for Amperometric Chemical Sensor. Sensors Wei-Song Wang, Wei-Ting Kuo, Hong-Yi Huang, Ching-Hsing Luo
2009	C	`conf`	0.5V 160-MHz 260uW all digital phase-locked loop. DDECS Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng
2009	C	`conf`	Analysis and optimization of ring oscillator using sub-feedback scheme. DDECS Hong-Yi Huang, Fu-Chien Tsai
2009	J	`jnl`	Wireless Body Sensor Network With Adaptive Low-Power Design for Biometrics and Healthcare Applications. IEEE Syst. J. Shih-Lun Chen, Ho-Yin Lee, Chiung-An Chen, Hong-Yi Huang, Ching-Hsing Luo
2008	—	`conf`	A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator. SoCC Hong-Yi Huang, Li-Wei Huang, Wei-Sheng Tseng, Chih-Yuan Hsu
2008	—	`conf`	All digital time-to-digital converter using single delay-locked loop. SoCC Hong-Yi Huang, Yi-Jui Tsai, Kung-Liang Ho, Chan-Yu Lin
2008	—	`conf`	CMOS bulk input current switch logic circuit. ICECS Hong-Yi Huang, Chun-Tsai Hung, Sheng-Chia Chiang
2008	C	`conf`	Dual band LNA/mixer using conjugate matching for implantable biotelemetry. ISCAS Wei-Chen Huang, Chen-Ming Hsu, Chien-Ming Lee, Hong-Yi Huang, Ching-Hsing Luo
2008	J	`jnl`	Frequency multiplier using 50% duty cycle corrector. IEICE Electron. Express Hong-Yi Huang, Chia-Ming Liang
2008	C	`conf`	Low-power 50% duty cycle corrector. ISCAS Hong-Yi Huang, Chia-Ming Liang, Shi-Jia Sun
2008	—	`conf`	Piecewise linear curvature-compensated CMOS bandgap reference. ICECS Hong-Yi Huang, Ru-Jie Wang, Shih-Chiang Hsu
2008	—	`conf`	Simultaneous bidirectional transceiver with impedance matching. ICECS Hong-Yi Huang, Ruei-Iun Pu, Ming-Ta Lee
2007	C	`conf`	A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme. ISCAS Hong-Yi Huang, Sheng-Da Wu, Yi-Jui Tsai
2007	—	`conf`	All-Digital PLL Using Pulse-Based DCO. ICECS Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng
2006	C	`conf`	1-99% input duty 50% output duty cycle corrector. ISCAS Hong-Yi Huang, Chia-Ming Liang, Wei-Ming Chiu
2006	C	`conf`	High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit. ISCAS Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu
2006	C	`conf`	On-chip bidirectional transceiver. ISCAS Hong-Yi Huang, Ching-Chieh Wu, Sen-Da Wu
2005	—	`conf`	A 64-MHz~1920-MHz programmable spread-spectrum clock generator. ISCAS (4) Hong-Yi Huang, Sheng-Fen Ho, Li-Wei Huang
2004	J	`jnl`	A low-jitter mutual-correlated pulsewidth control loop circuit. IEEE J. Solid State Circuits Wei-Ming Lin, Hong-Yi Huang
2004	—	`conf`	A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs. ISCAS (1) Chun-Jen Huang, Hong-Yi Huang
2004	J	`jnl`	Design and application of CMOS bulk input scheme. IEEE J. Solid State Circuits Hong-Yi Huang, Jing-Fu Lin
2004	J	`jnl`	Interconnect accelerating techniques for sub-100-nm gigascale systems. IEEE Trans. Very Large Scale Integr. Syst. Hong-Yi Huang, Shih-Lun Chen
2003	—	`conf`	A high-bandwidth wireless infrared receiver with feedforward offset extractor. ISCAS (1) Chin-Shan Hsieh, Hong-Yi Huang, Jeng-Dang Juan, Ruey-Nan Yeh
2002	—	`conf`	A time-delay-integration CMOS readout circuit for IR scanning. ICECS Fu-Kai Tsai, Hong-Yi Huang, Li-Kuo Dai, Cheng-Der Chiang, Ping-Kuo Weng, Yung-Chung Chin
2002	—	`conf`	CMOS bulk input technique. ISCAS (3) Hong-Yi Huang, Jing-Fu Lin
2002	—	`conf`	High-speed receivers for on-chip interconnections in deep-submicron process. ICECS Hong-Yi Huang, Shih-Lun Chen
2002	—	`conf`	Input isolated sense amplifiers. ISCAS (4) Hong-Yi Huang, Shih-Lun Chen
2002	—	`conf`	Low-power 2P2N SRAM with column hidden refresh. ISCAS (4) Hong-Yi Huang, Hsuan-Yi Su
2002	—	`conf`	Multiple bulk input differential logic. APCCAS (1) Hong-Yi Huang, Jing-Fu Lin
2002	—	`conf`	Threshold triggers and accelerator for deep submicron interconnection. APCCAS (2) Hong-Yi Huang, Shih-Lun Chen
2001	—	`conf`	High-speed CMOS logic circuits in capacitor coupling technique. ISCAS (4) Hong-Yi Huang, Teng-Neng Wang
1995	C	`conf`	Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu
1994	C	`conf`	New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems. ISCAS Hong-Yi Huang, Chung-Yu Wu
1993	J	`jnl`	Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic. IEEE J. Solid State Circuits Chung-Yu Wu, Hong-Yi Huang
1993	C	`conf`	Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications. ISCAS Hong-Yi Huang, Chung-Yu Wu