Hong-June Park

126 papers A* 1A 1C 1Misc 1Journal 82Unranked 40
YearRankTypeTitle / Venue / Authors
2025 J jnl
Area-Efficient Variable-Gain Delta-Sigma Modulator Achieving 11.5-dB Dynamic Range Improvement by Sharing Capacitors in the First-Stage Integrator.
IEEE Access
Yeon-Tae Choi, Hong-June Park
2024 J jnl
A PAM-4 Crosstalk Compensation Receiver Using an RC Circuit per Pin for 4×24 Gb/s/Pin Single-Ended DRAM Interface.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ho-Jun Kim, Sung-Yong Cho, Tae-Young Oh, Hong-June Park
2023 Misc conf
Pitch Mark Detection from Noisy Speech Waveform Using Wave-U-Net.
ICASSP
Hyun-Joon Nam, Hong-June Park
2021 J jnl
A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Sooeun Lee, Jaeyoung Seo, Changyoon Han, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2021 J jnl
A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface.
IEEE Trans. Circuits Syst. II Express Briefs
Min-Kyun Chae, Hye-Jung Kwon, Seung-Jun Bae, Nam-Jong Kim, Hong-June Park
2020 J jnl
A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jahyun Koo, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2020 J jnl
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels.
IEEE Trans. Very Large Scale Integr. Syst.
Jaeyoung Seo, Jaehyun Ko, Kyunghyun Lim, Sooeun Lee, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2020 J jnl
A Body Channel Communication Technique Utilizing Decision Feedback Equalization.
IEEE Access
Ji-Hoon Lee, Jaehyun Ko, Kwangmin Kim, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2020 J jnl
A pattern-dependent injection-locked CDR for clock-embedded signaling.
Microelectron. J.
Jaehyeong Hong, Dong Hoon Baek, Hyunwoo Son, Cheolmin Ahn, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2020 J jnl
An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss.
IEEE Trans. Circuits Syst.
Cheolmin Ahn, Jaehyeong Hong, Jongshin Shin, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2020 A* conf
GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design.
DAC
Seungho Han, Sungyu Jeong, Chanho Kim, Hong-June Park, Byungsub Kim
2020 J jnl
Low-Power Small-Area Inverter-Based DSM for MEMS Microphone.
IEEE Trans. Circuits Syst.
Seong-Eun Cho, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2019 J jnl
A 0.0043-mm
IEEE J. Solid State Circuits
Minseob Lee, Shinwoong Kim, Hong-June Park, Jae-Yoon Sim
2019 — conf
A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna.
VLSI Circuits
Cheonhoo Jeon, Jahyun Koo, Kyongsu Lee, Su-Kyoung Kim, Sei Kwang Hahn, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2019 J jnl
A 192-pW Voltage Reference Generating Bandgap- $V_{\text{th}}$ With Process and Temperature Dependence Compensation.
IEEE J. Solid State Circuits
Youngwoo Ji, Jungho Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2019 — conf
A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect.
ISSCC
Youngwoo Ji, Jungho Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2019 J jnl
A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation.
IEEE Trans. Biomed. Circuits Syst.
Hyunwoo Son, Hwasuk Cho, Jungho Lee, Seongun Bae, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2019 J jnl
A Quadrature RC Oscillator With Noise Reduction by Voltage Swing Control.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jahyun Koo, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2019 J jnl
Introduction to the Special Section on the 2018 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits
Hong-June Park, Jae-Yoon Sim, Robert Chen-Hao Chang
2018 — conf
A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC.
ISSCC
Minseob Lee, Shinwoong Kim, Hwasuk Cho, Jahyun Koo, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2018 — conf
A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiency.
ASP-DAC
Ji-Hoon Lee, Kwangmin Kim, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2018 — conf
A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces.
ISSCC
Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jaehyun Ko, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2018 — conf
A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic.
ASP-DAC
Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2018 J jnl
A Search Algorithm for the Worst Operation Scenario of a Cross-Point Phase-Change Memory Utilizing Particle Swarm Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Kwangmin Kim, Seokjoon Kang, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2018 J jnl
A Study on Bandgap Reference Circuit With Leakage-Based PTAT Generation.
IEEE Trans. Very Large Scale Integr. Syst.
Youngwoo Ji, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2018 J jnl
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface.
IEEE J. Solid State Circuits
Il-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2018 — conf
A low-power wide dynamic-range current readout circuit for biosensors.
ASP-DAC
Hyunwoo Son, Hwasuk Cho, Jahyun Koo, Youngwoo Ji, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2018 J jnl
An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications.
IEEE J. Solid State Circuits
Seungnam Choi, Hwan-Seok Ku, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2018 J jnl
An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching.
IEEE J. Solid State Circuits
Minsoo Choi, Sooeun Lee, Myungguk Lee, Ji-Hoon Lee, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2018 J jnl
An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.
IEEE Trans. Biomed. Circuits Syst.
Hwasuk Cho, Hyunwoo Son, Kihwan Seong, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2017 — conf
23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS.
ISSCC
Il-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2017 — conf
5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop.
ISSCC
Jahyun Koo, Kyoung-sik Moon, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2017 — conf
5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit.
ISSCC
Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2017 — conf
8.7 A 0.0047mm
ISSCC
Hwasuk Cho, Kihwan Seong, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2017 — conf
A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links.
A-SSCC
Myungguk Lee, Seungho Han, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2017 J jnl
A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Seunghwan Hong, Shinwoong Kim, Seungnam Choi, Hwasuk Cho, Jaehyeong Hong, Young Hun Seo, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2017 J jnl
A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors.
IEEE Trans. Biomed. Circuits Syst.
Hyunwoo Son, Hwasuk Cho, Jahyun Koo, Youngwoo Ji, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2017 J jnl
A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop.
IEEE Trans. Circuits Syst. II Express Briefs
Young-Ho Choi, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2017 J jnl
A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seungnam Choi, Yunjae Suh, Joohyun Lee, Jinkyu Kim, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2017 J jnl
A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation.
IEEE Trans. Biomed. Circuits Syst.
Yoon-Jee Kim, Sung-Eun Cho, Ji-Yong Um, Min-Kyun Chae, Jihoon Bang, Jongkeun Song, Taeho Jeon, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2017 J jnl
All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface.
IEEE Trans. Very Large Scale Integr. Syst.
Kihwan Seong, Won-Cheol Lee, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2017 J jnl
An Approximate Transfer Function Model of Two Serially Connected Heterogeneous Transmission Lines.
IEEE Trans. Circuits Syst. II Express Briefs
Jaeyoung Seo, Minsoo Choi, Sanquan Song, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2017 J jnl
Investigation on the Worst Read Scenario of a ReRAM Crossbar Array.
IEEE Trans. Very Large Scale Integr. Syst.
Yelim Youn, Kwangmin Kim, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2016 J jnl
A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seungnam Choi, Hyunwoo Son, Jongshin Shin, Sang-Hyun Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2016 J jnl
A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC.
IEEE J. Solid State Circuits
Shinwoong Kim, Seunghwan Hong, Kapseok Chang, Hyungsik Ju, Jaewook Shin, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2016 J jnl
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.
IEEE Trans. Circuits Syst. I Regul. Pap.
Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2016 J jnl
A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement.
IEEE J. Solid State Circuits
Seungho Han, Sooeun Lee, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2016 J jnl
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs.
IEEE Trans. Circuits Syst. II Express Briefs
Ji-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae-Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2016 J jnl
A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC.
J. Circuits Syst. Comput.
Dong-Woo Jee, Yunjae Suh, Hong-June Park, Jae-Yoon Sim
2016 J jnl
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits
Soo-Min Lee, Ji-Hoon Lim, Il-Min Yi, Young Jae Jang, Hae-Kang Jung, Kyunghoon Kim, Dae-Han Kwon, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2016 — conf
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.
VLSI Circuits
Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Young Jae Jang, Young-Chul Cho, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2016 — conf
A low-power LDO circuit with a fast load regulation.
APCCAS
Young Jae Jang, Seong-Eun Cho, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2016 — conf
All-synthesizable 6Gbps voltage-mode transmitter for serial link.
A-SSCC
Young-Ho Choi, Kihwan Seong, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2016 — conf
All-synthesizable transmitter driver and data recovery circuit for USB2.0 interface.
ISOCC
Kihwan Seong, Won-Cheol Lee, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2015 — conf
5.7 A 29nW bandgap reference circuit.
ISSCC
Jongmi Lee, Youngwoo Ji, Seungnam Choi, Young-Chul Cho, Seong-Jin Jang, Joo-Sun Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2015 A conf
A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design.
ICCAD
Sooeun Lee, Gunbok Lee, Jae-Yoon Sim, Hong-June Park, Wee Sang Park, Byungsub Kim
2015 J jnl
A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer.
IEEE Trans. Biomed. Circuits Syst.
Ji-Yong Um, Yoon-Jee Kim, Seong-Eun Cho, Min-Kyun Chae, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2015 J jnl
An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap.
Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2014 — conf
2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface.
ISSCC
Dong Hoon Baek, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2014 — conf
2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology.
ISSCC
Seungho Han, Sooeun Lee, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2014 — conf
24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area.
ISSCC
Ji-Yong Um, Eun-Woo Song, Yoon-Jee Kim, Seong-Eun Cho, Min-Kyun Chae, Jongkeun Song, Bae-Hyung Kim, Seunghun Lee, Jihoon Bang, Youngil Kim, Kyungil Cho, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2014 C conf
A 0.4 V driving multi-touch capacitive sensor with the driving signal frequency set to (n+0.5) times the inverse of the LCD VCOM noise period.
ISCAS
Jae-Seung Lee, Dong-Hee Yeo, Sang-Soo Lee, Hye-Jung Kwon, Jae-Yoon Sim, Byungsub Kim, Hong-June Park
2014 J jnl
A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation.
IEEE Trans. Circuits Syst. II Express Briefs
Hyunsoo Ha, Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2014 J jnl
A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination.
IEEE Trans. Circuits Syst. II Express Briefs
Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2014 — conf
A voltage-scalable 10-b pipelined ADC with current-mode amplifier.
CICC
Yunjae Suh, Seungnam Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2014 J jnl
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits
Soo-Min Lee, Il-Min Yi, Hae-Kang Jung, Hyunbae Lee, Yong-Ju Kim, Yunsaing Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2014 J jnl
An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array.
IEEE Trans. Biomed. Circuits Syst.
Ji-Yong Um, Yoon-Jee Kim, Seong-Eun Cho, Min-Kyun Chae, Jongkeun Song, Bae-Hyung Kim, Seung-Hun Lee, Jihoon Bang, Youngil Kim, Kyungil Cho, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2014 J jnl
An Approximate Closed-Form Channel Model for Diverse Interconnect Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim
2014 J jnl
Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current.
IEEE Trans. Circuits Syst. II Express Briefs
Hye-Jung Kwon, Jae-Seung Lee, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2014 J jnl
Current-Mode Transceiver for Silicon Interposer Channel.
IEEE J. Solid State Circuits
Seung-Hun Lee, Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2013 J jnl
A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Yunjae Suh, Jongmi Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2013 — conf
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX.
ISSCC
Soo-Min Lee, Jong-Hoon Kim, Jong-Sam Kim, Yunsaing Kim, Hyunbae Lee, Jae-Yoon Sim, Hong-June Park
2013 J jnl
A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS.
IEEE J. Solid State Circuits
Jun-Seok Kim, Young Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim
2013 J jnl
A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation.
IEEE J. Solid State Circuits
Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2013 J jnl
A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ji-Yong Um, Yoon-Jee Kim, Eun-Woo Song, Jae-Yoon Sim, Hong-June Park
2013 J jnl
A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL.
IEEE J. Solid State Circuits
Dong-Woo Jee, Yunjae Suh, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2013 J jnl
A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface.
IEEE Trans. Circuits Syst. II Express Briefs
Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2012 — conf
A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling.
CICC
Hyunsoo Ha, Yunjae Suh, Seon-Kyoo Lee, Hong-June Park, Jae-Yoon Sim
2012 J jnl
A 1.25 ps Resolution 8b Cyclic TDC in 0.13 µm CMOS.
IEEE J. Solid State Circuits
Young Hun Seo, Jun-Seok Kim, Hong-June Park, Jae-Yoon Sim
2012 J jnl
A 1.9-GHz Fractional-N Digital PLL With Subexponent ΔΣ TDC and IIR-Based Noise Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs
Dong-Woo Jee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2012 J jnl
A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC.
IEEE J. Solid State Circuits
Dong-Woo Jee, Young Hun Seo, Hong-June Park, Jae-Yoon Sim
2012 — conf
A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation.
ISSCC
Seon-Kyoo Lee, Hyunsoo Ha, Hong-June Park, Jae-Yoon Sim
2012 J jnl
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines.
IEEE J. Solid State Circuits
Hae-Kang Jung, Il-Min Yi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park
2012 — conf
A fractional-N frequency divider for SSCG using a single dual-modulus integer divider and a phase interpolator.
ISOCC
Young-Ho Choi, Jae-Yoon Sim, Hong-June Park
2012 — conf
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.
ISSCC
Young-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Bae Lee, Joo-Sun Choi, Hong-June Park, Jae-Yoon Sim
2012 — conf
An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits.
ISOCC
Il-Min Yi, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park
2011 J jnl
5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump.
IEEE Trans. Circuits Syst. II Express Briefs
Jong-Hoon Kim, Jung-Bum Shin, Jae-Yoon Sim, Hong-June Park
2011 — conf
A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering.
ISSCC
Dong-Woo Jee, Yunjae Suh, Hong-June Park, Jae-Yoon Sim
2011 J jnl
A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL.
IEEE J. Solid State Circuits
Young-Sang Kim, Seon-Kyoo Lee, Hong-June Park, Jae-Yoon Sim
2011 J jnl
A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL.
IEEE Trans. Circuits Syst. II Express Briefs
Hyung-Joon Chi, Young-Ho Choi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park, Jong-Jin Lim, Pil-Sung Kang, Bu-Yeol Lee, Jin-Cheol Hong, Hee-Sub Lee
2011 J jnl
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface.
IEEE J. Solid State Circuits
Seon-Kyoo Lee, Seung-Jin Park, Hong-June Park, Jae-Yoon Sim
2011 J jnl
A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface.
IEEE J. Solid State Circuits
Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park
2011 J jnl
A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition.
J. Electr. Comput. Eng.
Seon-Kyoo Lee, Young-Sang Kim, Hong-June Park, Jae-Yoon Sim
2011 — conf
A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio.
A-SSCC
Hye-Jung Kwon, Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park
2011 — conf
Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC.
A-SSCC
Ji-Yong Um, Jae-Hwan Kim, Jae-Yoon Sim, Hong-June Park
2011 — conf
Time-interleaved sample clock generator for ultrasound beamformer application.
ISOCC
Jae-Hwan Kim, Ji-Yong Um, Jae-Yoon Sim, Hong-June Park
2010 J jnl
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS.
IEEE J. Solid State Circuits
Seon-Kyoo Lee, Young Hun Seo, Hong-June Park, Jae-Yoon Sim
2010 — conf
A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS.
ISSCC
Seon-Kyoo Lee, Young Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim
2010 J jnl
A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength.
IEEE Trans. Circuits Syst. II Express Briefs
Young Hun Seo, Young-Sang Kim, Hong-June Park, Jae-Yoon Sim
2010 J jnl
A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration.
IEICE Trans. Electron.
Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park
2010 J jnl
A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage Using VCDL and Time-to-Digital Converter.
IEICE Trans. Electron.
Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park
2010 — conf
A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel.
CICC
Jun-Hyun Bae, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park
2010 — conf
A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines.
CICC
Hae-Kang Jung, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park
2010 J jnl
An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation.
IEICE Trans. Electron.
Young-Sang Kim, Yunjae Suh, Hong-June Park, Jae-Yoon Sim
2009 J jnl
A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park
2009 J jnl
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control.
IEEE J. Solid State Circuits
Hae-Kang Jung, Kyoungho Lee, Jong-Sam Kim, Jae-Jin Lee, Jae-Yoon Sim, Hong-June Park
2009 — conf
A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate.
ISSCC
Seon-Kyoo Lee, Young-Sang Kim, Hyunsoo Ha, Young Hun Seo, Hong-June Park, Jae-Yoon Sim
2009 J jnl
A Distortion-Free General Purpose LVDS Driver.
IEICE Trans. Electron.
Seung-Jin Park, Young Hun Seo, Hong-June Park, Jae-Yoon Sim
2009 J jnl
An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kwang-Hee Choi, Jung-Bum Shin, Jae-Yoon Sim, Hong-June Park
2008 — conf
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration.
ISSCC
Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Jae-Yoon Sim, Hong-June Park
2008 J jnl
A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface.
IEEE Trans. Circuits Syst. II Express Briefs
Sang-Hune Park, Kwang-Hee Choi, Jung-Bum Shin, Jae-Yoon Sim, Hong-June Park
2008 — conf
A low-voltage OP amp with digitally controlled algorithmic approximation.
CICC
Dong-Woo Jee, Seung-Jin Park, Hong-June Park, Jae-Yoon Sim
2008 J jnl
Deadzone-Minimized Systematic Offset-Free Phase Detectors.
IEICE Trans. Electron.
Young-Sang Kim, Yunjae Suh, Hong-June Park, Jae-Yoon Sim
2007 — conf
A 40-to-800MHz Locking Multi-Phase DLL.
ISSCC
Young-Sang Kim, Seung-Jin Park, Yong-Sub Kim, Dong-Bi Jang, Seh-Woong Jeong, Hong-June Park, Jae-Yoon Sim
2007 J jnl
An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator.
IEICE Trans. Electron.
Young-Chan Jang, Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park
2007 — conf
An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface.
CICC
Jun-Hyun Bae, Jin-Ho Seo, Hwan-Seok Yeo, Jae-Whui Kim, Jae-Yoon Sim, Hong-June Park
2006 J jnl
A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control.
IEEE Trans. Circuits Syst. II Express Briefs
Young-Chan Jang, Jun-Hyun Bae, Hong-June Park
2006 J jnl
A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation.
IEEE J. Solid State Circuits
Seok-Woo Choi, Hyun-Bae Lee, Hong-June Park
2005 J jnl
A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme.
IEEE J. Solid State Circuits
Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Hong-June Park
2005 J jnl
An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications.
IEICE Trans. Electron.
Jang-Jin Nam, Hong-June Park
2004 J jnl
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs.
IEEE J. Solid State Circuits
Young-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee, Kyo-Won Jin, Kyeong-Sik Min, Jin-Yong Chung, Hong-June Park
2003 — conf
A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation.
CICC
Young-Soo Sohn, Seung-Jun Bae, Hong-June Park, Changhyun Kim, Soo-In Cho
2003 J jnl
Two-phase boosted voltage generator for low-voltage DRAMs.
IEEE J. Solid State Circuits
Seong-Ik Cho, Jung-Hwan Lee, Hong-June Park, Gyu-Ho Lim, Young-Hee Kim
2002 J jnl
A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme.
IEEE J. Solid State Circuits
Jae-Yoon Sim, Jang-Jin Nam, Young-Soo Sohn, Hong-June Park, Chang-Hyun Kim, Soo-In Cho
1999 J jnl
A 1-Gb/s bidirectional I/O buffer using the current-mode scheme.
IEEE J. Solid State Circuits
Jae-Yoon Sim, Young-Soo Sohn, Seung-Chan Heo, Hong-June Park, Soo-In Cho
1985 J jnl
An Empirical Model for the Threshold Voltage of Enhancement NMOSFET's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hong-June Park, Choong-Ki Kim