Hojin Kee

15 papers C 1Misc 2Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2017 J jnl
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis.
Int. J. Reconfigurable Comput.
Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
2016 — conf
FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis.
Sarnoff Symposium
Swapnil Mhaske, Hojin Kee, Tai Ly, Predrag Spasojevic
2015 — conf
A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation.
Sarnoff Symposium
Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
2015 J jnl
A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R.
CoRR
Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
2015 — conf
High-Throughput FPGA-Based QC-LDPC Decoder Architecture.
VTC Fall
Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
2015 J jnl
High-Throughput FPGA-based QC-LDPC Decoder Architecture.
CoRR
Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic
2014 — conf
Rapid and high-level constraint-driven prototyping using lab VIEW FPGA.
GlobalSIP
Hojin Kee, Swapnil Mhaske, David Uliana, Adam Arnesen, Newton Petersen, Taylor L. Riché, Dustyn Blasig, Tai Ly
2012 J jnl
Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware.
J. Signal Process. Syst.
Hojin Kee, Chung-Ching Shen, Shuvra S. Bhattacharyya, Ian C. Wong, Yong Rao, Jacob Kornerup
2011 J jnl
Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs.
J. Signal Process. Syst.
Nimish Sane, Hojin Kee, Gunasekaran S. Seetharaman, Shuvra S. Bhattacharyya
2010 — conf
Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs.
ICSAMOS
Hojin Kee, Shuvra S. Bhattacharyya, Jacob Kornerup
2010 Misc conf
FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques.
ICASSP
Hojin Kee, Shuvra S. Bhattacharyya, Ian C. Wong, Yong Rao
2010 C conf
Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs.
International Symposium on Rapid System Prototyping
Hsiang-Huang Wu, Hojin Kee, Nimish Sane, William Plishker, Shuvra S. Bhattacharyya
2010 — —
Systematic Exploration of Trade-Offs between Application Throughput and Hardware Resource Requirements in DSP Systems.
Hojin Kee
2009 — conf
Resource-efficient acceleration of 2-dimensional Fast Fourier Transform computations on FPGAs.
ICDSC
Hojin Kee, Shuvra S. Bhattacharyya, Newton Petersen, Jacob Kornerup
2008 Misc conf
Systematic generation of FPGA-based FFT implementations.
ICASSP
Hojin Kee, Newton Petersen, Jacob Kornerup, Shuvra S. Bhattacharyya