Hitoshi Tanaka

20 papers B 1Journal 16Unranked 2
YearRankTypeTitle / Venue / Authors
2024 — conf
Automatic Generation of Tactile Graphics of Characters to Support Handwriting of Blind Individuals.
ICCHP (1)
Shunnosuke Sonobe, Hitoshi Tanaka, Akio Fujiyoshi
2022 J jnl
Deep Learning-enabled Detection and Classification of Bacterial Colonies using a Thin Film Transistor (TFT) Image Sensor.
CoRR
Yuzhu Li, Tairan Liu, Hatice Ceylan Koydemir, Hongda Wang, Keelan O'Riordan, Bijie Bai, Yuta Haga, Junji Kobashi, Hitoshi Tanaka, Takaya Tamaru, Kazunori Yamaguchi, Aydogan Ozcan
2021 J jnl
Advanced Machine Learning Techniques for Predicting Nha Trang Shorelines.
IEEE Access
Cheng Yin, Le Thanh Binh, Duong Tran Anh, Son T. Mai, Anh Le, Van-Hau Nguyen, Van-Chien Nguyen, Nguyen Xuan Tinh, Hitoshi Tanaka, Nguyen Trung Viet, Long Dinh Nguyen, Trung Q. Duong
2021 J jnl
Using Hybrid Wavelet-Exponential Smoothing Approach for Streamflow Modeling.
Complex.
Vahid Nourani, Hessam Najafi, Alireza Babaeian Amini, Hitoshi Tanaka
2015 J jnl
A remark on two generalized Orlicz-Morrey spaces.
J. Approx. Theory
Sadek Gala, Yoshihiro Sawano, Hitoshi Tanaka
2015 J jnl
Influence of Polymer Gate Dielectrics on p-Channel and n-Channel Formation of Fluorene-type Polymer Light-emitting Transistors.
IEICE Trans. Electron.
Hirotake Kajii, Masato Ise, Hitoshi Tanaka, Takahiro Ohtomo, Yutaka Ohmori
2011 B conf
Estimating damage-mitigation level of collision-prevention support braking.
Intelligent Vehicles Symposium
Keisuke Suzuki, Hitoshi Tanaka, Yoshiki Miichi, Masami Aga
2007 J jnl
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme.
IEEE J. Solid State Circuits
Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura
2007 — book
Ultra-Low Voltage Nano-Scale Memories
Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka
2006 — conf
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme.
ISSCC
Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura
2005 J jnl
Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications.
IEICE Trans. Electron.
Kouji Tsunoda, Akira Sato, Hiroko Tashiro, Toshiro Nakanishi, Hitoshi Tanaka
2003 J jnl
A concepts-of-sentences associative neural network.
Syst. Comput. Jpn.
Hitoshi Tanaka, Jingtao Huang, Masafumi Hagiwara
2003 J jnl
Visualization of large-scale internal seiche in Lake Inawashiro.
J. Vis.
Hitoshi Tanaka, Yutaka Fujita, Hiroto Yamaji
1999 J jnl
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.
IEEE J. Solid State Circuits
Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura
1997 J jnl
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip.
IEEE J. Solid State Circuits
Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome
1995 J jnl
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.
IEEE J. Solid State Circuits
Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda
1994 J jnl
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs.
IEEE J. Solid State Circuits
Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa
1991 J jnl
An experimental 1.5-V 64-Mb DRAM.
IEEE J. Solid State Circuits
Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh
1991 J jnl
Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM.
IEEE J. Solid State Circuits
Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki
1990 J jnl
A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier.
IEEE J. Solid State Circuits
Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto