Hitesh Shrimali

41 papers C 9Misc 3Journal 14Unranked 15
YearRankTypeTitle / Venue / Authors
2025 — conf
Current Bleeder-Based Mixer with -8.4 dB FoM, 10 dB NF, 18.5 dB Conversion Gain at 4.6 GHz.
ICECS
Sachin Kumar, Hitesh Shrimali
2025 — conf
Design of a Current-to-Frequency Converter with 0.18 pJ and 334 Hz/nA in 180 nm BCD-SOI.
PRIME
Puneet K. Mishra, Mohammad Waris, Sanjeev Mehta, R. Shrestha, Hitesh Shrimali
2024 C conf
A 12.7 Bit Accurate and 5.3nJ·µV
ISCAS
Saurabh Dhiman, Hitesh Shrimali
2024 — conf
A 5.4mW 12GHz Quadrature VCO using current reusing technique in 28nm CMOS technology.
ICCCNT
Zahid Rashid Sheikh, Taranveer Kaur, Rajasekhar Nagulapalli, Hitesh Shrimali, Mahendra Sakare
2024 — conf
A 66dBΩ 5 GHz and 44.88 √Hz/(pA·pW) Inductorless TIA in 65 nm CMOS.
MIXDES
Azhar Yaseen N. J, Shivdeep, Sahil Sharma, Hitesh Shrimali, Devarshi Mrinal Das
2024 Misc conf
An On-chip Thermoelectric Cooler Controller With Improved Driving Current of 2 A at 0.5 Ω Load.
VLSID
Sowmyashree S, Hitesh Shrimali
2024 J jnl
Corrigendum to "On minimizing charge injection error using multi-dummy switches with enhanced linearity" [Integration volume 97 (2024) 102175].
Integr.
Saurabh Dhiman, Hitesh Shrimali
2024 J jnl
On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity.
Integr.
Saurabh Dhiman, Hitesh Shrimali
2023 Misc conf
A Low Noise Bandgap Reference with 0.89 V Vref, 0.88 μVrms noise and 80 dB of PSRR.
VLSID
Sowmyashree S, Hitesh Shrimali
2023 — conf
Fully Monolithic 1A Thermoelectric Cooler Controller with 90% Efficiency.
ICECS
Sowmyashree S, Hitesh Shrimali
2022 J jnl
Design and implementation of a second order PLL based frequency synthesizer for implantable medical devices.
Integr.
B. Dinesh Kumar, Hitesh Shrimali
2022 J jnl
Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters.
IEEE Access
Muhammed Suhail Illikkal, Jai Narayan Tripathi, Vijender Kumar Sharma, Hitesh Shrimali, Ramachandra Achar
2022 J jnl
Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations.
IEEE Access
Kumar Sambhav Pandey, Hitesh Shrimali
2021 C conf
A Low-Power Quadrature LC-Oscillator Using Core-and-Coupling Current-Reuse.
ISCAS
B. Dinesh Kumar, Hitesh Shrimali, Nagarjuna Nallam
2021 — conf
Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters due to Periodic Fluctuations.
NEWCAS
Puneet Arora, Jai Narayan Tripathi, Hitesh Shrimali
2021 — conf
Design of CMOS Device Process Sensor in 28 nm FD-SOI with 2 % of Frequency Spread.
ICECS
Gowtham Peringattu Kalarikkal, Rohit Goel, Hitesh Shrimali
2021 J jnl
Digitally Assisted Secondary Switch-and-Compare Technique for a SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs
Ashish Joshi, Hitesh Shrimali, Satinder K. Sharma
2021 — conf
Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC.
MWSCAS
Navneet Gupta, Hitesh Shrimali, Adam Makosiej, Andrei Vladimirescu, Amara Amara
2020 J jnl
A Discrete-Time MOS Parametric Amplifier-Based Chopped Signal Demodulator.
IEEE Trans. Very Large Scale Integr. Syst.
Ashish Joshi, Hitesh Shrimali, Satinder K. Sharma
2020 C conf
Design and Analysis of a Low PSIJ, Energy Efficient Bootstrapped Driver for Space Application.
ISCAS
Saurabh Dhiman, Vijender Kumar Sharma, Hitesh Shrimali
2020 J jnl
Design of hybrid flash-SAR ADC using an inverter based comparator in 28 nm CMOS.
Microelectron. J.
B. Dinesh Kumar, Sumit K. Pandey, Navneet Gupta, Hitesh Shrimali
2020 J jnl
Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix.
IEEE Open J. Circuits Syst.
Vijender Kumar Sharma, Jai Narayan Tripathi, Hitesh Shrimali
2020 J jnl
Reduced switching mode for SAR ADCs: analysis and design of SAR A-to-D algorithm with periodic standby mode circuit components.
IET Circuits Devices Syst.
Ashish Joshi, Hitesh Shrimali, Satinder K. Sharma
2019 C conf
A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS.
ISCAS
B. Dinesh Kumar, Hitesh Shrimali, Navneet Gupta
2019 J jnl
A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers.
IEEE Access
Jai Narayan Tripathi, Muhammed Suhail Illikkal, Hitesh Shrimali, Ramachandra Achar
2019 C conf
An Ultra-Fast Parallel Prefix Adder.
ARITH
Kumar Sambhav Pandey, B. Dinesh Kumar, Neeraj Goel, Hitesh Shrimali
2019 C conf
Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator.
ISCAS
Vijender Kumar Sharma, B. Dinesh Kumar, Muhammed Suhail Illikkal, Jai Narayan Tripathi, Navneet Gupta, Hitesh Shrimali
2019 — conf
Design of HV-CMOS Detectors in BCD Technology with Noise and Crosstalk Measurements.
ICECS
Indu Yadav, Ashish Joshi, Ettore Ruscino, Valentino Liberali, Attilio Andreazza, Hitesh Shrimali
2019 Misc conf
Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process.
VLSID
Indu Yadav, Ashish Joshi, Ettore Ruscino, Valentino Liberali, Attilio Andreazza, Hitesh Shrimali
2019 — conf
Energy Efficient Bootstrapped Driver for a Particle Detector in 180 nm SOI Technology.
APCCAS
Saurabh Dhiman, Indu Yadav, Hitesh Shrimali
2018 — conf
Design of a Third Order Butterworth Gm-C Filter for EEG Signal Detection Application.
MIXDES
Ankita Deo, Sumit K. Pandey, Ashish Joshi, Satinder K. Sharma, Hitesh Shrimali
2018 C conf
The Capacitively Coupled Chopper Stabilized Amplifier with a DTPA based Demodulator.
ISCAS
Ashish Joshi, Hitesh Shrimali, Satinder K. Sharma
2017 — conf
Distortion analysis for a DC-DC buck converter.
ISOCC
Vijender Kumar Sharma, Hitesh Shrimali, Jai Narayan Tripathi, Rakesh Malik
2017 — conf
Nonlinear modeling and analysis of buck converter using volterra series.
ICECS
Hitesh Shrimali, Vijender Kumar Sharma, Jai Narayan Tripathi, Rakesh Malik
2017 J jnl
Systematic design approach for a gain boosted telescopic OTA with cross-coupled capacitor.
IET Circuits Devices Syst.
Ashish Joshi, Hitesh Shrimali, Satinder K. Sharma
2016 — conf
The pole-zero doublet: A cascode operational amplifier with cross coupled capacitor.
MWSCAS
Ashish Joshi, Indu Yadav, Satinder K. Sharma, Hitesh Shrimali
2015 J jnl
A technique to linearize the discrete-time parametric amplifier.
Microelectron. J.
Hitesh Shrimali, Shouri Chatterjee
2014 — conf
The start-up circuit for a low voltage bandgap reference.
ICECS
Hitesh Shrimali, Valentino Liberali
2011 C conf
11 GHz UGBW Op-amp with feed-forward compensation technique.
ISCAS
Hitesh Shrimali, Shouri Chatterjee
2011 J jnl
Distortion Analysis of a Three-Terminal MOS-Based Discrete-Time Parametric Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Hitesh Shrimali, Shouri Chatterjee
2011 C conf
Third order harmonic cancellation technique for a parametric amplifier.
ISCAS
Hitesh Shrimali, Shouri Chatterjee