Hisakatsu Yamaguchi

25 papers A 1Journal 10Unranked 14

Year	Rank	Type	Title / Venue / Authors
2021	A	`conf`	Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management. DATE Hisakatsu Yamaguchi, Makiko Ito, Katsuhiro Yoda, Atsushi Ike
2019	—	`conf`	Event-Driven Model for High Speed End-to-End Simulations of Transmission System with Non-Linear Optical Elements and Cascaded Clock-and-Data Recovery Circuits. VLSI-DAT Jun Matsui, Hisakatsu Yamaguchi
2018	J	`jnl`	Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs. IEEE J. Solid State Circuits Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
2018	J	`jnl`	On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR. IEEE J. Solid State Circuits Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
2017	—	`conf`	6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS. ISSCC Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
2017	—	`conf`	6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance. ISSCC Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
2017	J	`jnl`	A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS. IEEE J. Solid State Circuits Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
2017	—	`conf`	Jitter injection for on-chip jitter measurement in PI-based CDRs. CICC Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
2016	—	`conf`	3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. ISSCC Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
2016	—	`conf`	A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. VLSI Circuits Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka
2014	—	`conf`	A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. VLSIC Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura
2014	—	`conf`	F6: Energy-efficient I/O design for next-generation systems. ISSCC Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon
2013	—	`conf`	F3: Emerging technologies for wireline communication. ISSCC Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi
2013	—	`conf`	Session 2 overview: Ultra-high-speed transceivers and equalizers. ISSCC Ken Chang, Hisakatsu Yamaguchi
2012	—	`conf`	10-40 Gb/s I/O design for data communications. ISSCC Ken Chang, Tony Chan Carusone, Ali Sheikholeslami, Bob Payne, Miki Moyal, John T. Stonick, Hisakatsu Yamaguchi
2010	J	`jnl`	A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. IEEE J. Solid State Circuits Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa
2010	—	`conf`	A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. ISSCC Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh
2010	—	`conf`	A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. ISSCC Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto
2008	J	`jnl`	20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. IEEE J. Solid State Circuits Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
2008	J	`jnl`	Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI. IEEE Trans. Circuits Syst. I Regul. Pap. Marcus van Ierssel, Hisakatsu Yamaguchi, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
2007	J	`jnl`	18-GHz Clock Distribution Using a Coupled VCO Array. IEICE Trans. Electron. Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
2006	J	`jnl`	Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. IEICE Trans. Electron. Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa
2005	—	`conf`	A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process. CICC Yoshiyasu Doi, Syunitirou Masaki, Takaya Chiba, Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura
2005	J	`jnl`	A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization. IEEE J. Solid State Circuits Hirohito Higashi, Syunitirou Masaki, Masaya Kibune, Satoshi Matsubara, Takaya Chiba, Yoshiyasu Doi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Hirotaka Tamura
2003	J	`jnl`	A CMOS multichannel 10-Gb/s transceiver. IEEE J. Solid State Circuits Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura