Hiroyuki Yotsuyanagi

71 papers A 1B 1C 1Misc 4Journal 14Unranked 50
YearRankTypeTitle / Venue / Authors
2025 J jnl
An Implementation of Delay Testable Boundary Scan and Post-Bond Test Results in a 3D IC.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hiroyuki Yotsuyanagi, Keigo Takami, Masaki Hashizume
2025 — conf
Software-Defined Secure Island for Testing Chiplet Systems.
ATS
Hisashi Okamoto, Senling Wang, Hiroshi Kai, Hiroyuki Yotsuyanagi, Yoshinobu Higami, Tianming Ni, Tai Song, Hiroshi Takahashi, Xiaoqing Wen
2025 — conf
Test Point Insertion for an Approximate Multiplier Using Enhanced Static Segment Method to Reduce Test Patterns and Overdetection.
ITC-Asia
Takuya Kishimoto, Hiroyuki Yotsuyanagi
2024 — conf
Detectability of Resistive Open Defects with Analog Relaxation Oscillators Under Unit-to-Unit Variations of Dies.
3DIC
Yuya Yamahashi, Yuto Ohtera, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume
2024 — conf
Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs.
ITC-Asia
Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen
2023 — conf
On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults.
ITC-Asia
Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
2022 — conf
Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators.
ATS
Masao Ohmatsu, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume
2020 J jnl
Fault-Aware Dependability Enhancement Techniques for Flash Memories.
IEEE Trans. Very Large Scale Integr. Syst.
Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume, Hiroyuki Yotsuyanagi
2019 — conf
Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes.
3DIC
Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2019 — conf
On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection.
3DIC
Toshiaki Satoh, Hiroyuki Yotsuyanagi, Masaki Hashizume
2019 — conf
On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC.
ITC-Asia
Shuya Kikuchi, Hiroyuki Yotsuyanagi, Masaki Hashizume
2018 J jnl
A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs.
IEICE Trans. Inf. Syst.
Fara Ashikin, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Zvi Roth
2018 C conf
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification.
IOLTS
Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume
2018 — conf
Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design.
ATS
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume
2017 — conf
A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume.
ISCIT
Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2017 — conf
A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type.
DFT
Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2017 J jnl
Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi
2017 — conf
Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories.
ATS
Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume, Hiroyuki Yotsuyanagi
2017 — conf
On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects.
ISCIT
Yuuya Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi
2017 — conf
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs.
ATS
Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu
2016 J jnl
A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs.
IEICE Trans. Inf. Syst.
Widianto, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu, Zvi Roth
2015 — conf
Electrical interconnect test method of 3D ICs by injected charge volume.
3DIC
Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2015 — conf
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit.
3DIC
Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2015 — conf
On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs.
3DIC
Hiroyuki Yotsuyanagi, Akihiro Fujiwara, Masaki Hashizume
2014 — conf
A built-in supply current test circuit for electrical interconnect tests of 3D ICs.
3DIC
Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2013 J jnl
On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan.
IEICE Trans. Inf. Syst.
Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Takanobu Nimiya, Masaki Hashizume
2013 J jnl
SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Kozo Kinoshita
2013 — conf
Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs.
Asian Test Symposium
Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2011 — conf
A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing.
Asian Test Symposium
Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Masaki Hashizume
2011 — conf
A built-in test circuit for open defects at interconnects between dies in 3D ICs.
3DIC
Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume
2011 — conf
A supply current testable register string DAC of decoder type.
ISCIT
Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi, Yukiya Miura
2011 — conf
Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture.
3DIC
Tomoaki Konishi, Hiroyuki Yotsuyanagi, Masaki Hashizume
2010 B conf
Current-based testable design of level shifters in liquid crystal display drivers.
ETS
Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita
2010 J jnl
Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops.
IEICE Trans. Inf. Syst.
Hiroyuki Yotsuyanagi, Masayuki Yamamoto, Masaki Hashizume
2010 — conf
Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code.
Asian Test Symposium
Masashi Ishikawa, Hiroyuki Yotsuyanagi, Masaki Hashizume
2009 Misc conf
A Novel Approach for Improving the Quality of Open Fault Diagnosis.
VLSI Design
Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
2009 Misc conf
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.
VLSI Design
Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu
2009 — conf
New Class of Tests for Open Faults with Considering Adjacent Lines.
Asian Test Symposium
Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume
2007 — conf
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines.
ATS
Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume
2007 — conf
Current Testable Design of Resistor String DACs.
ATS
Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura
2007 — conf
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.
DFT
Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
2006 — conf
A BIC Sensor Capable of Adjusting IDDQ Limit in Tests.
ATS
Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura
2006 — conf
Current Testable Design of Resistor String DACs.
DELTA
Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura
2005 — conf
Electric field for detecting open leads in CMOS logic circuits by supply current testing.
ISCAS (3)
Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
2005 J jnl
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees.
J. Electron. Test.
Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
2004 — conf
A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits.
DELTA
Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
2004 J jnl
A test circuit for pin shorts generating oscillation in CMOS logic circuits.
Syst. Comput. Jpn.
Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
2004 — conf
CMOS Open Fault Detection by Appearance Time of Switching Supply Current.
DELTA
Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi, Takeomi Tamesada
2004 — conf
I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment.
Asian Test Symposium
Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada
2004 J jnl
Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits.
IEICE Trans. Inf. Syst.
Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
2004 — conf
On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure.
DELTA
Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
2004 — conf
Practical Fault Coverage of Supply Current Tests for Bipolar ICs.
DELTA
Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
2004 J jnl
Test Sequence Generation for Test Time Reduction of IDDQ Testing.
IEICE Trans. Inf. Syst.
Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada
2003 — conf
A BIST Circuit for IDDQ Tests.
Asian Test Symposium
Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita
2003 — conf
Reducing Scan Shifts Using Folding Scan Trees.
Asian Test Symposium
Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
2002 — conf
Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits.
DELTA
Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada
2002 — conf
Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field.
DELTA
Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada
2002 — conf
Test Time Reduction for I DDQ Testing by Arranging Test Vectors.
Asian Test Symposium
Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada
2001 — conf
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application.
Asian Test Symposium
Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
2001 A conf
CMOS open defect detection by supply current test.
DATE
Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
2001 — conf
IDDQ Sensing Technique for High Speed IDDQ Testing.
Asian Test Symposium
Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita
2001 — conf
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States.
Asian Test Symposium
Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada
2001 — conf
Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field.
DFT
Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada
2000 — conf
High speed IDDQ test and its testability for process variation.
Asian Test Symposium
Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda
2000 — conf
Testability Analysis of IDDQ Testing with Large Threshold Value.
DFT
Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda
1999 — conf
Identification of Feedback Bridging Faults with Oscillation.
Asian Test Symposium
Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
1998 Misc conf
Undetectable Fault Removal of Sequential Circuits Based on Unreachable States.
VTS
Hiroyuki Yotsuyanagi, Kozo Kinoshita
1997 J jnl
Synthesis of Sequential Circuits by Redundancy Removal and Retiming.
J. Electron. Test.
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1995 Misc conf
Resynthesis for sequential circuits designed with a specified initial state.
VTS
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1995 J jnl
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement.
IEICE Trans. Inf. Syst.
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1995 — conf
Synthesis for Testability by Sequential Redundancy Removal Using Retiming.
FTCS
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita