Hiroyuki Yamauchi

62 papers A 1B 1C 2Journal 33Unranked 25

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Evaluating Digital Map Utilization and Interpretation Skills of Students. ISPRS Int. J. Geo Inf. Hiroyuki Yamauchi, Jiali Song, Takashi Oguchi, Takuro Ogura, Kotaro Iizuka
2023	—	`conf`	Graph Structure Exploration for Reinforcement Learning State Embedding - Train Tetris Agent with Graph Neural Network. ICECC Weijie Guan, Zhufeng Li, Hiroyuki Yamauchi
2023	—	`conf`	Image Recognition Accuracy, Number of Parameters and Computational Complexity Using Channel Reduction by Dimensional Compression and Attention Function. ICECC Zhufeng Li, Hiroyuki Yamauchi
2022	—	`conf`	A Machine Learning Based Fuel Consumption Saving Method with Time and Environment Dependency Aware Management. ICECC Peng Yu, Hiroyuki Yamauchi
2021	J	`jnl`	A Layer-Wise Ensemble Technique for Binary Neural Network. Int. J. Pattern Recognit. Artif. Intell. Jiazhen Xi, Hiroyuki Yamauchi
2019	J	`jnl`	A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier. IEEE J. Solid State Circuits Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi, Meng-Fan Chang
2019	J	`jnl`	A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. Circuits Syst. I Regul. Pap. Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang
2018	—	`conf`	A 28mn 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell. A-SSCC Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi, Meng-Fan Chang
2018	J	`jnl`	Development and operation of GIS exercise materials for undergraduate students. PeerJ Prepr. Hiroyuki Yamauchi, Takashi Oguchi, Yuichi S. Hayakawa, Toshikazu Seto
2017	J	`jnl`	A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme. IEEE J. Solid State Circuits Meng-Fan Chang, Chien-Fu Chen, Ting-Hao Chang, Chi-Chang Shuai, Yen-Yao Wang, Yi-Ju Chen, Hiroyuki Yamauchi
2016	—	`conf`	A filter design for blind deconvolution to decouple unknown RDF/RTN factors from complexly coupled SRAM margin variations. LASCAS Hiroyuki Yamauchi, Worawit Somha
2016	—	`conf`	A mutual rectification-interference avoidance technique with cascade filters for both downward-direction tailed-RDF deconvolution. SBCCI Hiroyuki Yamauchi, Worawit Somha
2015	—	`conf`	17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme. ISSCC Meng-Fan Chang, Chien-Fu Chen, Ting-Hao Chang, Chi-Chang Shuai, Yen-Yao Wang, Hiroyuki Yamauchi
2015	—	`conf`	A Phase Shifting Multiple Filter Design Methodology for Lucy-Richardson Deconvolution of Log-Mixtures Complex RTN Tail Distribution. SBCCI Hiroyuki Yamauchi, Worawit Somha
2015	—	`conf`	A filter design to increase accuracy of Lucy-Richardson deconvolution for analyzing RTN mixtures effects on VLSI reliability margin. SoCC Hiroyuki Yamauchi, Worawit Somha, Yuan-Qiang Song
2015	—	`conf`	Feedback gain phase alignment effects on convergence characteristics in Lucy-Richardson deconvolution for inversely predicting complex-shaped RTN distributions. MWSCAS Hiroyuki Yamauchi, Worawit Somha
2015	—	`conf`	Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designs. LATS Hiroyuki Yamauchi, Worawit Somha
2014	—	`conf`	A technique to solve issue of Richardson-Lucy deconvolution for analyzing RTN effects on SRAM margin variation. LASCAS Hiroyuki Yamauchi, Worawit Somha
2014	J	`jnl`	An RTN Variation Tolerant SRAM Screening Test Design with Gaussian Mixtures Approximations of Long-Tail Distributions. J. Electron. Test. Worawit Somha, Hiroyuki Yamauchi
2014	—	`conf`	Comparative study on deconvolution function dependencies of RTN/RDF effect estimation errors in analyzing sub-nm-scaled SRAM margins. MWSCAS Hiroyuki Yamauchi, Worawit Somha
2014	C	`conf`	Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variation. VLSI-SoC Hiroyuki Yamauchi, Worawit Somha
2014	—	`conf`	Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs. SoCC Hiroyuki Yamauchi, Worawit Somha
2013	J	`jnl`	A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms. IEEE J. Solid State Circuits Meng-Fan Chang, Chih-Sheng Lin, Wei-Cheng Wu, Ming-Pin Chen, Yen-Huei Chen, Zhe-Hui Lin, Shyh-Shyuan Sheu, Tzu-Kun Ku, Cha-Hsin Lin, Hiroyuki Yamauchi
2013	—	`conf`	A RTN variation tolerant guard band design for a deeper nanometer scaled SRAM screening test: Based on EM Gaussians mixtures approximations model of long-tail distributions. LATW Worawit Somha, Hiroyuki Yamauchi
2013	J	`jnl`	A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V IEEE J. Solid State Circuits Meng-Fan Chang, Ming-Bin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi
2013	—	`conf`	A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributions. ISVLSI Worawit Somha, Hiroyuki Yamauchi, Ma YuYu
2013	J	`jnl`	An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory. IEEE J. Solid State Circuits Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi
2013	—	`conf`	Convolution/deconvolution SRAM analyses for complex gamma mixtures RTN distributions. ICICDT Worawit Somha, Hiroyuki Yamauchi
2013	J	`jnl`	Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement. IEEE J. Solid State Circuits Shu-Meng Yang, Meng-Fan Chang, Chi-Chuang Chiang, Ming-Bin Chen, Hiroyuki Yamauchi
2012	—	`conf`	A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. VLSIC Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi
2012	J	`jnl`	Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM. IEEE J. Solid State Circuits Yen-Huei Chen, Shao-Yu Chou, Quincy Li, Wei-Min Chan, Dar Sun, Hung-Jen Liao, Ping Wang, Meng-Fan Chang, Hiroyuki Yamauchi
2012	—	`conf`	Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device. ASP-DAC Meng-Fan Chang, Ching-Hao Chuang, Min-Ping Chen, Lai-Fu Chen, Hiroyuki Yamauchi, Pi-Feng Chiu, Shyh-Shyuan Sheu
2011	J	`jnl`	A Large Sigma V IEEE J. Solid State Circuits Jui-Jen Wu, Yen-Hui Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi
2011	—	`conf`	An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory. ISSCC Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Shang-Chi Wu, Chia-En Huang, Han-Chao Lai, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi
2010	—	`conf`	A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications. ISSCC Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi
2010	J	`jnl`	A Differential Data-Aware Power-Supplied (D IEEE J. Solid State Circuits Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Yung-Chi Chen, Yen-Hui Chen, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi
2010	J	`jnl`	A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies. IEEE Trans. Very Large Scale Integr. Syst. Hiroyuki Yamauchi
2009	J	`jnl`	A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. IEEE J. Solid State Circuits Yen-Huei Chen, Gary Chan, Shao-Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi
2008	J	`jnl`	A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. IEEE J. Solid State Circuits Toshikazu Suzuki, Hiroyuki Yamauchi, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu
2008	J	`jnl`	An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics. IEEE Trans. Very Large Scale Integr. Syst. Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi
2007	J	`jnl`	A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Trans. Electron. Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami
2007	—	`conf`	A 45nm dual-port SRAM with write and read capability enhancement at low voltage. SoCC D. P. Wang, Hung-Jen Liao, Hiroyuki Yamauchi, Y. H. Chen, Y. L. Lin, S. H. Lin, D. C. Liu, Huan-Cheng Chang, W. Hwang
2007	J	`jnl`	A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. IEICE Trans. Electron. Yasue Yamamoto, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Shinichi Sumi, Yasuhiro Agata, Hirohito Kikukawa, Hiroyuki Yamauchi
2007	—	`conf`	A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme. CICC Toshikazu Suzuki, Hiroyuki Yamauchi, Katsuji Satomi, Hironori Akamatsu
2007	—	`conf`	SRAM. ISSCC Kevin Zhang, Hiroyuki Yamauchi
2006	J	`jnl`	A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage ( IEICE Trans. Electron. Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami
2006	J	`jnl`	A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. IEEE J. Solid State Circuits Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi
2005	J	`jnl`	0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. IEICE Trans. Electron. Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi
2005	J	`jnl`	A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. IEEE J. Solid State Circuits Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto
2005	J	`jnl`	A 400-MHz random-cycle dual-port interleaved DRAM (D IEEE J. Solid State Circuits Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi
2000	C	`conf`	A Method and Language for Constructing Multiagent Systems. ISMIS Hiroyuki Yamauchi, Setsuo Ohsuga
1999	—	`conf`	Incorporating Fuzzy Set Theory and Matrix Logic in Multi-Layer Logic - A Preliminary Consideration. RSFDGrC Hiroyuki Yamauchi, Setsuo Ohsuga
1997	J	`jnl`	A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. IEEE Trans. Very Large Scale Integr. Syst. Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
1996	A	`conf`	A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. ISLPED Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
1996	J	`jnl`	A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme. IEEE J. Solid State Circuits Hiroyuki Yamauchi, Akira Matsuzawa
1995	J	`jnl`	A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current. IEEE J. Solid State Circuits Hiroyuki Yamauchi, Tom Iwata, Akito Uno, Masanori Fukumoto, Tsutomu Fujita
1995	J	`jnl`	An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's. IEEE J. Solid State Circuits Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita
1993	J	`jnl`	A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's. IEEE J. Solid State Circuits Hiroyuki Yamauchi, Toshikazu Suzuki, Akihiro Sawada, Tohru Iwata, Toshiaki Tsuji, Masashi Agata, Takashi Taniguchi, Yoshinori Odake, Kazuyuki Sawada, Teruhito Ohnishi, Masanori Fukumoto, Tsutomu Fujita, Michihiro Inoue
1990	J	`jnl`	A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers. IEEE J. Solid State Circuits Hiroyuki Yamauchi, Toshiki Yabu, Takayoshi Yamada, Michihiro Inoue
1990	J	`jnl`	Losse Coupling of KAUS with Existing RDBMSs. Data Knowl. Eng. Hiroyuki Yamauchi, Setsuo Ohsuga
1985	J	`jnl`	Multi-Layer Logic - A Predicate Logic Including Data Structure as Knowledge Representation Language. New Gener. Comput. Setsuo Ohsuga, Hiroyuki Yamauchi
1980	B	`conf`	Processing Of Syntax And Semantics Of Natural Language By Predicate Logic Of Predicate Logic. COLING Hiroyuki Yamauchi