Hiroyuki Ochi - RankMe

75 papers A* 2A 6B 5C 3Misc 1Journal 28Unranked 30

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Small-Area CNN Inference Architecture with Bit-Serial Pipeline Datapath and Zero Skipping. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinya Hattori, Hiroyuki Ochi
2025	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroyuki Ochi
2023	J	`jnl`	A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor. IPSJ Trans. Syst. LSI Des. Methodol. Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi
2023	—	`conf`	Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments. SOCC Renya Makimoto, Takashi Imagawa, Hiroyuki Ochi
2023	—	`conf`	Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction. ASICON Xuanqi Li, Takashi Imagawa, Hiroyuki Ochi
2023	J	`jnl`	Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. IEICE Trans. Electron. Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
2022	—	`conf`	Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations. MWSCAS Yuki Abe, Kazutoshi Kobayashi, Hiroyuki Ochi
2022	—	`conf`	Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. COOL CHIPS Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
2021	A	`conf`	MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. DATE Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi
2021	—	`conf`	Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT. COOL CHIPS Takaki Urabe, Hiroyuki Ochi, Kazutoshi Kobayashi
2020	—	`conf`	33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
2018	J	`jnl`	Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto
2018	J	`jnl`	Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
2017	J	`jnl`	Area-Efficient LUT-Like Programmable Logic Using Atom Switch and Its Delay-Optimal Mapping Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshiki Higashi, Hiroyuki Ochi
2017	—	`conf`	Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain. SoCC Takashi Imagawa, Koki Honda, Hiroyuki Ochi
2017	—	`conf`	Selectable grained reconfigurable architecture (SGRA) and its design automation. SoCC Ryosuke Koike, Takashi Imagawa, Roberto Yusi Omaki, Hiroyuki Ochi
2016	B	`conf`	A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
2016	J	`jnl`	Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Kishimoto, Wataru Takahashi, Kazutoshi Wakabayashi, Hiroyuki Ochi
2015	—	`conf`	A -0.5V-input voltage booster circuit for on-chip solar cells in 0.18µm CMOS technology. ISCIT Tomoya Kimura, Hiroyuki Ochi
2015	J	`jnl`	An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. IEICE Trans. Electron. Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
2015	—	`conf`	Area-efficient LUT-like programmable logic using atom switch and its mapping algorithm. ISCIT Toshiki Higashi, Hiroyuki Ochi
2015	—	`conf`	Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera
2014	—	`conf`	Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits. ISQED Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi
2014	J	`jnl`	Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera
2013	J	`jnl`	A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis. IEICE Trans. Electron. Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	A	`conf`	A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. DATE Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	—	`conf`	Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis. ACM Great Lakes Symposium on VLSI Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	—	`conf`	High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA. ISQED Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	A	`conf`	Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. DATE Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi
2013	—	`conf`	Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye
2013	—	`conf`	Multi-trap RTN parameter extraction based on Bayesian inference. ISQED Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	J	`jnl`	Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element. IEICE Trans. Electron. Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	—	`conf`	Realization of frequency-domain circuit analysis through random walk. ASP-DAC Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	—	`conf`	Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation. SoCC Hiroyuki Ochi, Toshihiko Ota, Ataru Yamaoka, Hiromasa Watanabe, Yohei Kondo, Nobuyuki Tokuda, Hiroyuki Taguchi, Taketoshi Matsumoto, Tomoki Akai, Hikaru Kobayashi, Shigeki Imai
2012	J	`jnl`	A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2012	J	`jnl`	A high-throughput pipelined parallel architecture for JPEG XR encoding. ACM Trans. Embed. Comput. Syst. Hiroshi Tsutsui, Koichi Hattori, Hiroyuki Ochi, Yukihiro Nakamura
2012	J	`jnl`	Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2012	—	`conf`	Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices. ISQED Takashi Sato, Hiromitsu Awano, Hirofttmi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi
2011	—	`conf`	A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization. SoCC Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato
2011	—	`conf`	A fully pipelined implementation of Monte Carlo based SSTA on FPGAs. ISQED Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2011	—	`conf`	Acceleration of random-walk-based linear circuit analysis using importance sampling. ACM Great Lakes Symposium on VLSI Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2010	—	`conf`	A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. SoCC Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
2010	Misc	`conf`	Path clustering for adaptive test. VTS Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
2010	J	`jnl`	Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
2010	C	`conf`	Scan based process parameter estimation through path-delay inequalities. ISCAS Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
2010	A	`conf`	Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis. ICCAD Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2009	—	`conf`	A high-throughput pipelined architecture for JPEG XR encoding. ESTIMedia Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
2009	J	`jnl`	An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. Inf. Media Technol. Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura
2009	J	`jnl`	An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. IPSJ Trans. Syst. LSI Des. Methodol. Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura
2009	B	`conf`	Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye
2009	B	`conf`	Dynamic rate control for media streaming in high-speed mobile networks. WCNC Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, Yukihiro Nakamura
2009	J	`jnl`	Efficient Memory Organization Framework for JPEG2000 Entropy Codec. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroki Sugano, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura
2009	J	`jnl`	Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroki Sugano, Hiroyuki Ochi, Yukihiro Nakamura, Ryusuke Miyamoto
2009	—	`conf`	Hardware Architecture for HOG Feature Extraction. IIH-MSP Ryoji Kadota, Hiroki Sugano, Masayuki Hiromoto, Hiroyuki Ochi, Ryusuke Miyamoto, Yukihiro Nakamura
2009	B	`conf`	Hot-Swapping architecture extension for mitigation of permanent functional unit faults. FPL Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura
2008	—	`conf`	An architecture of photo core transform in HD photo coding system for embedded systems of various bandwidths. APCCAS Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
2008	J	`jnl`	Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
2007	J	`jnl`	A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
2007	—	`conf`	Home Appliance Control from Mobile Phones. CCNC Hiromitsu Sumino, Norihiro Ishikawa, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura, Yoshitaka Uchida
2007	—	`conf`	Implementation of AV Streaming System Using Peer-to-Peer Communication. CCNC Norihiro Ishikawa, Hiroshi Tsutsui, Jaehoon Yu, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, Takaaki Komura, Yoshitaka Uchida
2007	J	`jnl`	Network Processor for High-Speed Network and Quick Programming. J. Circuits Syst. Comput. Takahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura
2006	J	`jnl`	A Localization Scheme for Sensor Networks Based on Wireless Communication with Anchor Groups. IEICE Trans. Inf. Syst. Hiroyuki Ochi, Shigeaki Tagashira, Satoshi Fujita
2006	A	`conf`	Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices. FPGA Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
2006	C	`conf`	Efficient memory architecture for JPEG2000 entropy codec. ISCAS Hiroki Sugano, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura
2006	J	`jnl`	Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
2006	B	`conf`	Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells. FPL Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
2006	C	`conf`	Pedestrian Recognition in Far-Infrared Images by Combining Boosting-Based Detection and Skeleton-Based Stochastic Tracking. PSIVT Ryusuke Miyamoto, Hiroki Sugano, Hiroaki Saito, Hiroshi Tsutsui, Hiroyuki Ochi, Ken'ichi Hatanaka, Yukihiro Nakamura
2005	—	`conf`	A Localization Scheme for Sensor Networks based onWireless Communication with Anchor Groups. ICPADS (1) Hiroyuki Ochi, Shigeaki Tagashira, Satoshi Fujita
2005	J	`jnl`	An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tomonori Izumi, Shin'ichi Kouyama, Hiroyuki Ochi, Yukihiro Nakamura
2003	J	`jnl`	Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroyuki Ochi, Tatsuya Suzuki, Sayaka Matsunaga, Yoichi Kawano, Takao Tsuda
2002	J	`jnl`	Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takahiro Kakimoto, Hiroyuki Ochi, Takao Tsuda
2000	—	`conf`	A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. ASP-DAC Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Yeol Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda
1993	A	`conf`	Breadth-first manipulation of very large binary-decision diagrams. ICCAD Hiroyuki Ochi, Koichi Yasuoka, Shuzo Yajima
1991	A*	`conf`	Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. DAC Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima
1991	A*	`conf`	Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification. CAV Hiromi Hiraishi, Kiyoharu Hamaguchi, Hiroyuki Ochi, Shuzo Yajima