Hiroyuki Mizuno

45 papers A* 1A 2B 1C 2Journal 24Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A 20-GHz Low-Noise RF Pulse Generator for Silicon Quantum Computer with 137.4-fs Jitter. IEICE Trans. Electron. Takayasu Norimatsu, Yusuke Wachi, Takuji Miki, Yusuke Kanno, Ryozo Takahashi, Takashi Ogawa, Takeru Utsugi, Tomonori Sekiguchi, Makoto Nagata, Hiroyuki Mizuno
2025	J	`jnl`	Quantum Computer Architecture for Quantum Error Correction With Distributing Process to Multiple Temperature Layers. Concurr. Comput. Pract. Exp. Ryuji Ukai, Chihiro Yoshimura, Hiroyuki Mizuno
2025	J	`jnl`	e-person Architecture and Framework for Human-AI Co-adventure Relationship. CoRR Kanako Esaki, Tadayuki Matsumura, Yang Shao, Hiroyuki Mizuno
2024	—	`conf`	A cryogenic pulse shaper for spin qubit control utilizing 1ns-time-resolution ADCs on an active silicon interposer operating at sub-100 mK temperatures. A-SSCC Ryozo Takahashi, Yusuke Kanno, Takuji Miki, Nobuhiro Kusuno, Hiroyuki Mizuno, Makoto Nagata
2024	—	`conf`	AI-Facilitation for Consensus-Building by Virtual Discussion Using Large Language Models. PRICAI (2) Tadayuki Matsumura, Takeshi Kato, Yasuhiro Asa, Kanako Esaki, Ryuji Mine, Hiroyuki Mizuno
2024	J	`jnl`	Active Inference With Empathy Mechanism for Socially Behaved Artificial Agents in Diverse Situations. Artif. Life Tadayuki Matsumura, Kanako Esaki, Shao Yang, Chihiro Yoshimura, Hiroyuki Mizuno
2024	—	`conf`	Concatenated Continuous Driving for Extending Lifetime of Spin Qubits Towards a Scalable Silicon Quantum Computer. VLSI Technology and Circuits T. Kuno, Takeru Utsugi, N. Lee, T. Mine, I. Yanagi, S. Muraoka, R. Mizokuchi, Jun Yoneda, Tetsuo Kodera, T. Nakajima, A. J. Ramsay, N. Mertig, S. Saito, D. Hisamoto, R. Tsuchiya, Hiroyuki Mizuno
2024	J	`jnl`	Environment-Centric Active Inference. CoRR Kanako Esaki, Tadayuki Matsumura, Takeshi Kato, Shunsuke Minusa, Yang Shao, Hiroyuki Mizuno
2024	J	`jnl`	Generating Shuttling Procedures for Constrained Silicon Quantum Dot Array. CoRR Naoto Sato, Tomonori Sekiguchi, Takeru Utsugi, Hiroyuki Mizuno
2024	J	`jnl`	Response Style Characterization for Repeated Measures Using the Visual Analogue Scale. IEEE Access Shunsuke Minusa, Tadayuki Matsumura, Kanako Esaki, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno
2024	J	`jnl`	Response Style Characterization for Repeated Measures Using the Visual Analogue Scale. CoRR Shunsuke Minusa, Tadayuki Matsumura, Kanako Esaki, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno
2023	—	`conf`	Dynamical Perception-Action Loop Formation with Developmental Embodiment for Hierarchical Active Inference. IWAI Kanako Esaki, Tadayuki Matsumura, Shunsuke Minusa, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno
2023	J	`jnl`	Mixbiotic society measures: Assessment of community well-going as living system. CoRR Takeshi Kato, Junichi Miyakoshi, Tadayuki Matsumura, Ryuji Mine, Hiroyuki Mizuno, Yasuo Deguchi
2023	J	`jnl`	Mixbiotic society measures: Comparison of organizational structures based on communication simulation. CoRR Takeshi Kato, Junichi Miyakoshi, Tadayuki Matsumura, Yasuyuki Kudo, Ryuji Mine, Hiroyuki Mizuno, Yasuo Deguchi
2023	—	`conf`	Quantum Computer Architecture for Quantum Error Correction with Distributing Process to Multiple Temperature Layers. candar Ryuji Ukai, Chihiro Yoshimura, Hiroyuki Mizuno
2023	—	`conf`	Quantum Computing from Hype to Game Changer. VLSI Technology and Circuits Hiroyuki Mizuno
2023	J	`jnl`	Social Co-OS: Cyber-human social Co-operating system. IET Cyper-Phys. Syst.: Theory & Appl. Takeshi Kato, Yasuyuki Kudo, Junichi Miyakoshi, Misa Owa, Yasuhiro Asa, Takashi Numata, Ryuji Mine, Hiroyuki Mizuno
2023	J	`jnl`	The impact of individual information exchange strategies on the distribution of social wealth. CoRR Yang Shao, Hirokazu Atsumori, Tadayuki Matsumura, Kanako Esaki, Shunsuke Minusa, Hiroyuki Mizuno
2022	—	`conf`	Extended-Self Recognition for Autonomous Agent Based on Controllability and Predictability. SSCI Kanako Esaki, Tadayuki Matsumura, Chihiro Yoshimura, Hiroyuki Mizuno
2022	J	`jnl`	Mask Atari for Deep Reinforcement Learning as POMDP Benchmarks. CoRR Yang Shao, Quan Kong, Tadayuki Matsumura, Taiki Fuji, Kiyoto Ito, Hiroyuki Mizuno
2021	—	`conf`	Sensorimotor Visual Perception on Embodied System Using Free Energy Principle. PKDD/ECML Workshops (1) Kanako Esaki, Tadayuki Matsumura, Kiyoto Ito, Hiroyuki Mizuno
2021	J	`jnl`	Social Co-OS: Cyber-Human Social Co-Operating System. CoRR Takeshi Kato, Yasuyuki Kudo, Junichi Miyakoshi, Misa Owa, Yasuhiro Asa, Takashi Numata, Ryuji Mine, Hiroyuki Mizuno
2020	J	`jnl`	Sensorimotor Visual Perception on Embodied System Using Free Energy Principle. CoRR Kanako Esaki, Tadayuki Matsumura, Kiyoto Ito, Hiroyuki Mizuno
2016	J	`jnl`	A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing. IEEE J. Solid State Circuits Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2016	J	`jnl`	Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution. Int. J. Netw. Comput. Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2015	—	`conf`	24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing. ISSCC Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2015	—	`conf`	An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution. CANDAR Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2014	C	`conf`	Nonlinear reduced order modeling of plasticization cylinders. ACC Tomonori Sadamoto, Kenji Kashima, Hiroshi Morita, Hiroyuki Mizuno
2013	—	`conf`	Spatial computing architecture using randomness of memory cell stability under voltage control. ECCTD Chihiro Yoshimura, Masanao Yamaoka, Hidetaka Aoki, Hiroyuki Mizuno
2010	—	`conf`	A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima
2010	—	`conf`	Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. 3DIC Kiyoto Ito, Makoto Saen, Kenichi Osada, Tomoyuki Kodama, Hiroyuki Mizuno
2009	B	`conf`	Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara
2008	—	`conf`	An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. ISSCC Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara
2007	J	`jnl`	Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. IEEE J. Solid State Circuits Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie
2007	J	`jnl`	In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution. IEEE J. Solid State Circuits Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno
2006	—	`conf`	Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. ISSCC Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie
2006	A*	`conf`	Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno
2001	C	`conf`	Low-Voltage Embedded-RAM Technology: Present and Future. VLSI-SOC Kiyoo Itoh, Hiroyuki Mizuno
1999	J	`jnl`	A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. IEEE Trans. Very Large Scale Integr. Syst. Hiroyuki Mizuno, Koichiro Ishibashi
1999	J	`jnl`	An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. IEEE J. Solid State Circuits Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, Kunio Uchiyama
1999	A	`conf`	On the Use of Density Distribution of Keywords for Automated Generation of Hypertext Links from Arbitrary Parts of Documents. ICDAR Koichi Kise, Hiroyuki Mizuno, Masashi Yamaguchi, Keinosuke Matsumoto
1998	A	`conf`	A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. ISLPED Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi
1997	J	`jnl`	A 1-V programmable DSP for wireless communications [CMOS]. IEEE J. Solid State Circuits Wai Lee, Paul E. Landman, Brock Barton, Shigeshi Abiko, Hiroshi Takahashi, Hiroyuki Mizuno, Shigetoshi Muramatsu, Kenichi Tashiro, Masahiro Fusumada, Luat Pham, Frederic Boutaud, Emmanuel Ego, Girolamo Gallo, Hiep Tran, Carl Lemonds, Albert Shih, Mahalingam Nandakumar, Robert H. Eklund, Ih-Chin Chen
1996	J	`jnl`	A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. IEEE J. Solid State Circuits Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure
1996	J	`jnl`	Driving source-line cell architecture for sub-1-V high-speed low-power applications. IEEE J. Solid State Circuits Hiroyuki Mizuno, Takahiro Nagano