Hiroyuki Iwata

17 papers A* 1A 3B 1Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2025 A conf
A Novel Omnidirectional 3D Test Access Architecture for Advanced System-on-Wafer (SoW) Applications.
ITC
Hiroyuki Iwata, Sandeep Kumar Goel, Ankita Patidar, Fumiaki Takashima, Frank Lee
2024 A conf
Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs.
ITC
Hiroyuki Iwata, Mahmoud AbdAlwahab, Ron Press, Ohki Sugiura
2023 A conf
A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy.
ITC
Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee
2023 J jnl
Test Point Insertion for Multi-Cycle Power-On Self-Test.
ACM Trans. Design Autom. Electr. Syst.
Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2021 — conf
A Power Reduction Method for Scan Testing in Ultra-Low Power Designs.
ATS
Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2020 J jnl
FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST.
IEICE Trans. Inf. Syst.
Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2018 J jnl
Automotive Functional Safety Assurance by POST with Sequential Observation.
IEEE Des. Test
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
2018 — conf
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST.
ATS
Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2018 B conf
Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262.
ETS
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2017 — conf
A multichannel-near-infrared-spectroscopy-triggered robotic hand rehabilitation system for stroke patients.
ICORR
Jongseung Lee, Nobutaka Mukae, Jumpei Arata, Hiroyuki Iwata, Keiji Iramina, Koji Iihara, Makoto Hashizume
2016 — conf
Multi-configuration Scan Structure for Various Purposes.
ATS
Hiroyuki Iwata, Jun Matsushima
2016 — conf
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation.
ATS
Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
2012 — conf
An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms.
Asian Test Symposium
Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Masahiro Takakura
2011 — conf
Low Power Decompressor and PRPG with Constant Value Broadcast.
Asian Test Symposium
Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer
2008 J jnl
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
2007 A* conf
A DFT Method for Time Expansion Model at Register Transfer Level.
DAC
Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara
2005 — conf
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.
Asian Test Symposium
Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara