Hiroyuki Hara

26 papers B 1C 1Journal 12Unranked 12
YearRankTypeTitle / Venue / Authors
2016 — conf
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.
ISSCC
Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
2015 — conf
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.
ISSCC
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita
2013 J jnl
A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation.
IEICE Trans. Electron.
Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa
2012 — conf
An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation.
COOL Chips
Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa
2011 J jnl
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.
IEEE J. Solid State Circuits
Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki
2011 — conf
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS.
ISSCC
Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada
2011 — conf
A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications.
COOL Chips
Daisuke Taki, Tatsuo Shiozawa, Kuniaki Ito, Youichiro Shiba, Kouji Horisaki, Hirotsugu Kajihara, Toshiyuki Yamagishi, Masahiro Sekiya, Akira Yamaga, Tetsuya Fujita, Hiroyuki Hara, Masanori Kuwahara, Toshio Fujisawa, Yasuo Unekawa
2011 — conf
A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.
A-SSCC
Keiichi Kushida, Osamu Hirabayashi, Fumihiko Tachibana, Hiroyuki Hara, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Yuki Fujimura, Yusuke Niki, Miyako Shizuno, Shinichi Sasaki, Tomoaki Yabe
2010 — conf
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.
ISSCC
Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki
2008 — conf
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.
ISSCC
Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi
2008 — conf
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design.
CICC
Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada
2007 C conf
An automated runtime power-gating scheme.
ICCD
Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki
2007 J jnl
Pulse-Width Modulation with Current Uniformization for TFT-OLEDs.
IEICE Trans. Electron.
Mutsumi Kimura, Shigeki Sawamura, Masakazu Kato, Yuji Hara, Daisuke Suzuki, Hiroyuki Hara, Satoshi Inoue
2006 J jnl
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling.
IEEE J. Solid State Circuits
Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama
2006 J jnl
Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki
2006 — conf
Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems.
ASP-DAC
Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake, Yoshiki Tsukiboshi, Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami
2005 — conf
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI.
CICC
Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki
2005 J jnl
Classification of Driving Methods for TFT-OLEDs and Novel Proposal Using Time Ratio Grayscale and Current Uniformization.
IEICE Trans. Electron.
Mutsumi Kimura, Yuji Hara, Hiroyuki Hara, Tomoyuki Okuyama, Satoshi Inoue, Tatsuya Shimoda
2004 — conf
Low temperature polycrystalline silicon TFT fingerprint sensor with integrated comparator circuit.
ESSCIRC
Hiroyuki Hara, Mikio Sakurai, Mitsutoshi Miyasaka, Simon W. B. Tam, Satoshi Inoue, Tatsuya Shimoda
2001 J jnl
A bitline leakage compensation scheme for low-voltage SRAMs.
IEEE J. Solid State Circuits
Ken-ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda
1999 B conf
Wireless and IP integrated system architectures for broadband mobile multimedia services.
WCNC
Masahiro Umehira, Masamitsu Nakura, Makoto Umeuchi, Junichi Murayama, Takaaki Murai, Hiroyuki Hara
1996 J jnl
A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications.
IEEE J. Solid State Circuits
Akilesh Parameswar, Hiroyuki Hara, Takayasu Sakurai
1994 J jnl
A 200 MHz 13 mm
IEEE J. Solid State Circuits
Masataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai
1992 J jnl
0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file.
IEEE J. Solid State Circuits
Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba
1991 J jnl
0.5- mu m 2 M-transistor BiPNMOS channelless gate array.
IEEE J. Solid State Circuits
Hiroyuki Hara, Takayasu Sakurai, Makoto Noda, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Yoshinori Watanabe
1991 J jnl
A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network.
IEEE J. Solid State Circuits
Kenji Sakaue, Yasuro Shobatake, Masahiko Motoyama, Yoshinari Kumaki, Satoru Takatsuka, Shigeru Tanaka, Hiroyuki Hara, Kouji Matsuda, Shuji Kitaoka, Makoto Noda, Youichiro Niitsu, Masayuki Norishima, Hiroshi Momose, Kenji Maeguchi, Manabu Ishibe, Shoichi Shimizu, Toshikazu Kodama