Hiroto Yasuura

117 papers A* 5A 16B 3C 8Misc 2Journal 33Unranked 49

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	ASP-DAC 2017 keynote speech I-3: Design of society: Beyond digital system design. ASP-DAC Hiroto Yasuura
2012	J	`jnl`	A Selective Replacement Method for Timing-Error-Predicting flip-Flops. J. Circuits Syst. Comput. Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida
2012	—	`conf`	Guidelines for mitigating NBTI degradation in on-chip memories. ISCIT Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida
2012	C	`conf`	Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	WiP Abstract: Estimation of Electric Power Consumption of Individuals by Observing People's Activity. ICCPS Atsushi Shimada, Shigeru Takano, Shigeaki Tagashira, Rin-Ichiro Taniguchi, Hiroto Yasuura
2011	Misc	`conf`	An Anonymous Authentication Protocol with Single-database PIR. AISC Toru Nakamura, Shunsuke Inenaga, Kensuke Baba, Daisuke Ikeda, Hiroto Yasuura
2011	C	`conf`	Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	J	`jnl`	Password Based Anonymous Authentication with Private Information Retrieval. J. Digit. Inf. Manag. Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Kensuke Baba, Hiroto Yasuura
2011	J	`jnl`	Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI. IEICE Trans. Electron. Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
2011	J	`jnl`	Towards Modeling Stored-value Electronic Money Systems. Inf. Media Technol. Shunsuke Inenaga, Kenichirou Oyama, Hiroto Yasuura
2010	C	`conf`	A Replacement Strategy for Canary Flip-Flops. PRDC Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
2010	—	`conf`	An Identifiable Yet Unlinkable Authentication System with Smart Cards for Multiple Services. ICCSA (4) Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Kensuke Baba, Hiroto Yasuura
2010	B	`conf`	An Information Platform for Low-Literate Villagers. AINA Ashir Ahmed, Lutfe Kabir, Hiroto Yasuura
2010	—	`conf`	An RTOS in hardware for energy efficient software-based TCP/IP processing. SASP Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura
2010	J	`jnl`	Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. J. Signal Process. Syst. Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
2010	—	`conf`	Signal probability control for relieving NBTI in SRAM cells. ISQED Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
2009	J	`jnl`	An Optimization Technique for Low-Energy Embedded Memory Systems. IPSJ Trans. Syst. LSI Des. Methodol. Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
2009	—	`conf`	Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe
2009	J	`jnl`	Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment. IEICE Trans. Electron. Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura
2009	—	`conf`	Large Scale Business-academia Collaboration in Master Education Course. CSEDU (2) Noriaki Sakamoto, Mitsuaki Fukase, Tsunenori Mine, Shigeru Kusakabe, Tsuneo Nakanishi, Yoichi Omori, Mohammad Mesbah Uddin, Keijiro Araki, Akira Fukuda, Hiroto Yasuura, Teruaki Kitasuka
2009	Misc	`conf`	Modeling Costs of Access Control with Various Key Management Systems. PDPTA Tomomi Yamasaki, Shunsuke Inenaga, Daisuke Ikeda, Hiroto Yasuura
2009	J	`jnl`	Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion. IPSJ Trans. Syst. LSI Des. Methodol. Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
2009	—	`conf`	Towards Modeling Stored-value Electronic Money Systems. NaBIC Shunsuke Inenaga, Kenichirou Oyama, Hiroto Yasuura
2008	—	`conf`	A Framework of Authentic Post-Issuance Program Modification for Multi-Application Smart Cards. ICWN Mohammad Mesbah Uddin, Salahuddin Muhammad Salim Zabir, Yasunobu Nohara, Hiroto Yasuura
2008	J	`jnl`	A Multi-Application Smart Card System with Authentic Post-Issuance Program Modification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mohammad Mesbah Uddin, Yasunobu Nohara, Daisuke Ikeda, Hiroto Yasuura
2008	C	`conf`	A Note on Biometrics-based Authentication with Portable Device. SECRYPT Shinsuke Ohtsuka, Satoshi Kawamoto, Shigeru Takano, Kensuke Baba, Hiroto Yasuura
2008	B	`conf`	A Secure High-Speed Identification Scheme for RFID Using Bloom Filters. ARES Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura
2008	J	`jnl`	A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V Microelectron. J. Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
2008	—	`conf`	Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura
2008	—	`conf`	Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
2007	—	`conf`	A Door Access Control System with Mobile Phones. PWC Tomomi Yamasaki, Toru Nakamura, Kensuke Baba, Hiroto Yasuura
2007	—	`conf`	A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
2007	—	`conf`	A low complexity and energy efficient dynamic channel allocation algorithm for multiuser OFDM. WTS Adil El Bourichi, Hiroto Yasuura
2007	—	`conf`	Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTIMedia Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
2007	—	`conf`	Unlinkability and Real World Constraints in RFID Systems. PerCom Workshops Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura
2006	—	`conf`	An Energy Characterization Framework for Software-Based Embedded Systems. ESTIMedia Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah
2006	—	`conf`	On Authentication between Human and Computer. PerCom Workshops Takahiro Watanabe, Yasunobu Nohara, Kensuke Baba, Sozo Inoue, Hiroto Yasuura
2006	B	`conf`	Systematic Error Detection for RFID Reliability. ARES Sozo Inoue, Hiroto Yasuura, Daisuke Hagiwara
2006	J	`jnl`	Unlinkable Identification for Large-scale RFID Systems. Inf. Media Technol. Yasunobu Nohara, Toru Nakamura, Kensuke Baba, Sozo Inoue, Hiroto Yasuura
2005	—	`conf`	A variation-aware low-power coding methodology for tightly coupled buses. ASP-DAC Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura
2005	—	`conf`	An RFID-based multi-service system for supporting conference events. AMT Takahiro Watanabe, Sozo Inoue, Hiroto Yasuura, Jun Sasaki, Yasushi Aoki, Kazumi Akimoto
2005	J	`jnl`	Bitwidth Optimization for Low Power Digital FIR Filter Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kosuke Tarumi, Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura
2005	—	`conf`	Quantitative evaluation of unlinkable ID matching schemes. WPES Yasunobu Nohara, Sozo Inoue, Kensuke Baba, Hiroto Yasuura
2005	J	`jnl`	Special Section on Papers Selected from AP-ASIC 2004. IEICE Trans. Electron. Hiroto Yasuura, Shoji Kawahito
2005	—	`conf`	Toward Unlinkable ID Management for Multi-Service Environments. PerCom Workshops Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura
2004	—	`conf`	Digitally Named World: Challenges for New Social Infrastructures. ISQED Hiroto Yasuura
2003	C	`conf`	A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. DSD Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura
2003	J	`jnl`	Leakage Power Reduction for Battery-Operated Portable Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yun Cao, Hiroto Yasuura
2003	J	`jnl`	Pre-Route Power Analysis Techniques for SoC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Yamada, Takeshi Sakamoto, Shinji Furuichi, Mamoru Mukuno, Yoshifumi Matsushita, Hiroto Yasuura
2003	—	`ed.`	Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 ASP-DAC Hiroto Yasuura
2003	—	`conf`	Quality-driven design by bitwidth optimization for video applications. ASP-DAC Yun Cao, Hiroto Yasuura
2003	J	`jnl`	Reduction of coupling effects by optimizing the 3-D configuration of the routing grid. IEEE Trans. Very Large Scale Integr. Syst. Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
2003	—	`conf`	Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid. ASP-DAC Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
2003	J	`jnl`	Routing Methodology for Minimizing Crosstalk in SoC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Yamada, Atsushi Sakai, Yoshifumi Matsushita, Hiroto Yasuura
2003	—	`conf`	Routing methodology for minimizing 1nterconnect energy dissipation. ACM Great Lakes Symposium on VLSI Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
2003	C	`conf`	Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. DSD Hiroto Yasuura
2003	J	`jnl`	Variable Pipeline Depth Processor for Energy Efficient Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura
2002	C	`conf`	A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA. DSD Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
2002	—	`conf`	A Power Minimization Technique for Arithmetic Circuits by Cell Selection. ASP-DAC/VLSI Design Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
2002	A	`conf`	A low-power digital matched filter for spread-spectrum systems. ISLPED Shoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
2002	—	`conf`	An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems. ISSS Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
2002	—	`conf`	Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. ISSS Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao
2002	—	`conf`	Optimization of Test Accesses with a Combined BIST and External Test Scheme. ASP-DAC/VLSI Design Makoto Sugihara, Hiroto Yasuura
2002	A	`conf`	Power analysis techniques for SoC with improved wiring models. ISLPED Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
2002	J	`jnl`	Quality-Driven Design for Video Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yun Cao, Hiroto Yasuura
2002	A	`conf`	Reducing access energy of on-chip data memory considering active data bitwidth. ISLPED Takanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura
2002	—	`conf`	Special Session: Security on SoC. ISSS Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys
2001	J	`jnl`	A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine. Genet. Program. Evolvable Mach. Barry Shackleford, Greg Snider, Richard J. Carter, Etsuko Okushi, Mitsuhiro Yasuda, Katsuhiko Seo, Hiroto Yasuura
2001	A	`conf`	A system-level energy minimization approach using datapath width optimization. ISLPED Yun Cao, Hiroto Yasuura
2001	J	`jnl`	Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Des. Test Comput. Takanori Okuma, Hiroto Yasuura, Tohru Ishihara
2000	A	`conf`	A Bus Delay Reduction Technique Considering Crosstalk. DATE Kei Hirose, Hiroto Yasuura
2000	A	`conf`	A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. DATE Tohru Ishihara, Hiroto Yasuura
2000	A	`conf`	An FPGA-based genetic algorithm machine (poster abstract). FPGA Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
2000	A	`conf`	Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. DATE Makoto Sugihara, Hiroto Yasuura, Hiroshi Date
2000	J	`jnl`	Editorial. Des. Autom. Embed. Syst. Hiroto Yasuura
2000	J	`jnl`	Flexible System LSI for Embedded Systems and Its Optimization Techniques. Des. Autom. Embed. Syst. Akihiko Inoue, Tohru Ishihara, Hiroto Yasuura
2000	—	`conf`	Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs. SBCCI Victor M. Goulart Ferreira, Hiroto Yasuura
2000	—	`conf`	One language or more?: how can we design an SoC at a system level? ASP-DAC Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
2000	—	`conf`	Variable size analysis and validation of computation quality. HLDVT Hajime Yamashita, Hiroto Yasuura, Eko Fajar, Yun Cao
1999	—	`conf`	Real-Time Task Scheduling for a Variable Voltage Processor. ISSS Takanori Okuma, Tohru Ishihara, Hiroto Yasuura
1998	A	`conf`	A novel test methodology for core-based system LSIs and a testing time minimization problem. ITC Makoto Sugihara, Hiroshi Date, Hiroto Yasuura
1998	J	`jnl`	Embedded System Design Using Soft-Core Processor and Valen-C. J. Inf. Sci. Eng. Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar
1998	—	`conf`	Instruction Encoding Techniques for Area Minimization of Instruction ROM. ISSS Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura
1998	A	`conf`	Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura
1998	—	`conf`	Module Selection Using Manufacturing Information. ASP-DAC Hiroyuki Tomiyama, Hiroto Yasuura
1998	—	`conf`	Power-Pro: Programmable Power Management Architecture. ASP-DAC Tohru Ishihara, Hiroto Yasuura
1998	A	`ed.`	Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998 ICCAD Hiroto Yasuura
1998	—	`conf`	Statistical Performance-Driven Module Binding in High-Level Synthesis. ISSS Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura
1998	A	`conf`	Voltage scheduling problem for dynamically variable voltage processors. ISLPED Tohru Ishihara, Hiroto Yasuura
1997	—	`conf`	A HW/SW co-design environment for multi-media equipments development using inverse problem. CODES Fumio Suzuki, Hisao Koizumi, M. Hiramine, K. Yamamoto, Hiroto Yasuura, K. Okino
1997	—	`conf`	A High-Performance Hardware Implementation of a Survival-Based Genetic Algorithm. ICONIP (1) Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
1997	J	`jnl`	Code placement techniques for cache miss rate reduction. ACM Trans. Design Autom. Electr. Syst. Hiroyuki Tomiyama, Hiroto Yasuura
1997	A*	`conf`	Memory-CPU Size Optimization for Embedded System Designs. DAC Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura
1997	A	`ed.`	Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997 ICCAD Ralph H. J. M. Otten, Hiroto Yasuura
1996	A	`conf`	Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. ISLPED Tohru Ishihara, Hiroto Yasuura
1996	J	`jnl`	On the Computational Power of Binary Decision Diagram with Redundant Variables. Formal Methods Syst. Des. Tetsuya Yamada, Hiroto Yasuura
1996	—	`conf`	Optimal Code Placement of Embedded Software for Instruction Caches. ED&TC Hiroyuki Tomiyama, Hiroto Yasuura
1996	—	`conf`	Size-Constrained Code Placement for Cache Miss Rate Reduction. ISSS Hiroyuki Tomiyama, Hiroto Yasuura
1995	J	`jnl`	A Proposal for a Co-design Method in Control Systems Using Combination of Models. IEICE Trans. Inf. Syst. Hisao Koizumi, Katsuhiko Seo, Fumio Suzuki, Yoshisuke Ohtsuru, Hiroto Yasuura
1995	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Hiroto Yasuura
1994	A*	`conf`	Design Reuse: Fact or Fiction? (Panel). DAC Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura
1993	A	`conf`	A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. International Conference on Supercomputing Takashi Hashimoto, Kazuaki J. Murakami, Tetsuo Hironaka, Hiroto Yasuura
1992	—	`conf`	Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura
1990	A	`conf`	Extraction of Functional Information from Combinatorial Circuits. ICCAD M. Ohmura, Hiroto Yasuura, Keikichi Tamaru
1990	C	`conf`	Formal semantics of UDL/I and its applications to CAD/DA tools. ICCD Hiroto Yasuura, Nagisa Ishiura
1990	A*	`conf`	NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. DAC Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima
1989	—	`conf`	Locally Computable Coding for Unary Operations. Concurrency: Theory, Language, And Architecture Hiroto Yasuura
1989	A*	`conf`	Semantics of a Hardware Design Language for Japanese Standardization. DAC Hiroto Yasuura, Nagisa Ishiura
1987	J	`jnl`	High-Speed Logic Simulation on Vector Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima
1987	J	`jnl`	On high-speed parallel algorithms using redundant coding. Syst. Comput. Jpn. Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima
1985	J	`jnl`	High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. IEEE Trans. Computers Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima
1984	—	`conf`	Hardware Algorithms for VLSI Systems. VLSI Engineering Hiroto Yasuura, Shuzo Yajima
1984	—	`conf`	On Parallel Computational Complexity of Unification. FGCS Hiroto Yasuura
1982	A*	`conf`	An Interactive Simulation System for structured logic design - ISS. DAC Takeshi Sakai, Yoshiyuki Tsuchida, Hiroto Yasuura, Yasushi Ooi, Yoshitsugu Ono, Hiroshi Kano, Shinji Kimura, Shuzo Yajima
1982	—	`conf`	Hardware Algorithms and Logic Design Automation. An Overview and Progress Report. RIMS Symposium on Software Science and Engineering Shuzo Yajima, Hiroto Yasuura
1982	J	`jnl`	The Parallel Enumeration Sorting Scheme for VLSI. IEEE Trans. Computers Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima
1981	J	`jnl`	Width and Depth of Combinational Logic Circuits. Inf. Process. Lett. Hiroto Yasuura