Hirotaka Tamura

87 papers A 2B 1C 1Misc 1Journal 41Unranked 41

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	MOCQA: A Multi-Core Optimizer for Constrained Quadratic Assignment. IEEE Access Mohammad Bagherbeik, Parastoo Ashtari, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2025	J	`jnl`	Performance of the Extended Ising Machine for the Quadratic Knapsack Problem. CoRR Haruka Akishima, Hirotaka Tamura, Kazue Kudo
2025	J	`jnl`	Sampling via Rejection-Free Partial Neighbor Search. Commun. Stat. Simul. Comput. Sigeng Chen, Jeffrey S. Rosenthal, Aki Dote, Hirotaka Tamura, Ali Sheikholeslami
2024	C	`conf`	Digital Annealing Engine for High-speed Solving of Constrained Binary Quadratic Problems on Multiple GPUs. ICCE Kentaro Katayama, Noboru Yoneoka, Kouichi Kanda, Hirotaka Tamura, Hiroshi Nakayama, Yasuhiro Watanabe
2024	J	`jnl`	Nebula: Network Enhanced Boltzmann Machine With Universal Local Search Architecture. IEEE Access Yasuhiro Watanabe, Hirotaka Tamura, Yuki Furue, Fang Yin
2024	J	`jnl`	Penalty Coefficient Adjustment Technique for Extended Ising Machines. IEEE Access Fang Yin, Hirotaka Tamura, Yuki Furue, Yasuhiro Watanabe
2023	J	`jnl`	Characterization of Locality in Spin States and Forced Moves for Optimizations. CoRR Yoshiki Sato, Makiko Konoshima, Hirotaka Tamura, Jun Ohkubo
2023	J	`jnl`	Efficient correlation-based discretization of continuous variables for annealing machines. CoRR Yuki Furue, Makiko Konoshima, Hirotaka Tamura, Jun Ohkubo
2023	J	`jnl`	Generating gradients in the energy landscape using rectified linear type cost functions for efficiently solving 0/1 matrix factorization in Simulated Annealing. CoRR Makiko Konoshima, Hirotaka Tamura, Yoshiyuki Kabashima
2023	J	`jnl`	Optimization via Rejection-Free Partial Neighbor Search. Stat. Comput. Sigeng Chen, Jeffrey S. Rosenthal, Aki Dote, Hirotaka Tamura, Ali Sheikholeslami
2022	A	`conf`	MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA. FPGA Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2022	—	`conf`	MAQO: A Scalable Many-Core Annealer for Quadratic Optimization. VLSI Technology and Circuits Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2021	J	`jnl`	Jump Markov chains and rejection-free Metropolis algorithms. Comput. Stat. Jeffrey S. Rosenthal, Aki Dote, Keivan Dabiri, Hirotaka Tamura, Sigeng Chen, Ali Sheikholeslami
2020	—	`conf`	A Hamiltonian Engine for Radiotherapy Optimization. EMBC Mehrdad Malekmohammadi, Keivan Dabiri, Joshua Mathews, Daryl Nazareth, Hirotaka Tamura, Ali Sheikholeslami
2020	—	`conf`	A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems. PPSN (1) Mohammad Bagherbeik, Parastoo Ashtari, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2020	J	`jnl`	Derivation of QUBO formulations for sparse estimation. CoRR Tomohiro Yokota, Makiko Konoshima, Hirotaka Tamura, Jun Ohkubo
2020	—	`conf`	Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications. ASP-DAC Satoshi Matsubara, Motomu Takatsu, Toshiyuki Miyazawa, Takayuki Shibasaki, Yasuhiro Watanabe, Kazuya Takemoto, Hirotaka Tamura
2020	J	`jnl`	Replica Exchange MCMC Hardware With Automatic Temperature Selection and Parallel Trial. IEEE Trans. Parallel Distributed Syst. Keivan Dabiri, Mehrdad Malekmohammadi, Ali Sheikholeslami, Hirotaka Tamura
2019	—	`conf`	A 30Gb/s 2x Half-Baud-Rate CDR. CICC Danny Yoo, Mohammad Bagherbeik, Wahid Rahman, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki
2019	—	`conf`	A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS. ISSCC Danny Yoo, Mohammad Bagherbeik, Wahid Rahman, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki
2018	J	`jnl`	Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs. IEEE J. Solid State Circuits Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
2018	J	`jnl`	On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR. IEEE J. Solid State Circuits Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
2018	J	`jnl`	Physics-inspired optimization for constraint-satisfaction problems using a digital annealer. CoRR Maliheh Aramon, Gili Rosenberg, Toshiyuki Miyazawa, Hirotaka Tamura, Helmut G. Katzgraber
2017	—	`conf`	6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS. ISSCC Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
2017	—	`conf`	6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance. ISSCC Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
2017	J	`jnl`	A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS. IEEE J. Solid State Circuits Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
2017	—	`conf`	Fast algorithm using summed area tables with unified layer performing convolution and average pooling. MLSP Akihiko Kasagi, Tsuguchika Tabaru, Hirotaka Tamura
2017	Misc	`conf`	Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine. CISIS Satoshi Matsubara, Hirotaka Tamura, Motomu Takatsu, Danny Yoo, Behraz Vatankhahghadim, Hironobu Yamasaki, Toshiyuki Miyazawa, Sanroku Tsukamoto, Yasuhiro Watanabe, Kazuya Takemoto, Ali Sheikholeslami
2017	—	`conf`	Jitter injection for on-chip jitter measurement in PI-based CDRs. CICC Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
2016	—	`conf`	24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR. OFC Yukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Jun Matsui, Takashi Shiraishi, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
2016	—	`conf`	3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. ISSCC Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
2016	—	`conf`	A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. VLSI Circuits Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka
2015	—	`conf`	22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI. ISSCC Yanfei Chen, Masaya Kibune, Asako Toda, Akinori Hayakawa, Tomoyuki Akiyama, Shigeaki Sekiguchi, Hiroji Ebe, Nobuhiro Imaizumi, Tomoyuki Akahoshi, Suguru Akiyama, Shinsuke Tanaka, Takasi Simoyama, Ken Morito, Takuji Yamamoto, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
2015	—	`conf`	22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS. ISSCC Takayuki Shibasaki, Yukito Tsunoda, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura
2015	—	`conf`	22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS. ISSCC Yukito Tsunoda, Takayuki Shibasaki, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura
2015	—	`conf`	25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs. OFC Yukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura
2015	J	`jnl`	A 3x blind ADC-based CDR for a 20 dB loss channel. IEEE Trans. Circuits Syst. I Regul. Pap. Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2015	J	`jnl`	A Reference-Less Single-Loop Half-Rate Binary CDR. IEEE J. Solid State Circuits Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2015	J	`jnl`	On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs. IEEE J. Solid State Circuits Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014	—	`conf`	A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. VLSIC Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura
2014	—	`conf`	A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. VLSIC Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
2014	—	`conf`	A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE. CICC Clifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014	J	`jnl`	An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset". IEEE Trans. Circuits Syst. I Regul. Pap. Ravi Shivnaraine, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014	—	`conf`	On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs. VLSIC Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014	A	`conf`	Optimizing effective interconnect capacitance for FPGA power reduction. FPGA Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
2013	—	`conf`	32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE. ISSCC Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura
2013	—	`conf`	32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. ISSCC Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura
2013	J	`jnl`	A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. IEEE J. Solid State Circuits Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura
2013	J	`jnl`	A Blind Baud-Rate ADC-Based CDR. IEEE J. Solid State Circuits Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013	—	`conf`	A blind baud-rate ADC-based CDR. ISSCC Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013	—	`conf`	An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection. CICC Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013	B	`conf`	Charge recycling for power reduction in FPGA interconnect. FPL Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
2013	—	`conf`	Design metrics for blind ADC-based wireline receivers. CICC Ali Sheikholeslami, Hirotaka Tamura
2011	—	`conf`	A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS. ISSCC Behrooz Abiri, Ravi Shivnaraine, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011	—	`conf`	A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS. ISSCC Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011	J	`jnl`	A 60-GHz Injection-Locked Frequency Divider Using Multi-Order IEICE Trans. Electron. Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda
2011	—	`conf`	A pattern-guided adaptive equalizer in 65nm CMOS. ISSCC Shayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2011	J	`jnl`	An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS. IEEE J. Solid State Circuits Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune
2010	J	`jnl`	A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker
2010	J	`jnl`	A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. IEEE J. Solid State Circuits Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa
2010	—	`conf`	A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. ISSCC Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh
2010	—	`conf`	A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS. CICC Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda
2010	J	`jnl`	A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
2010	—	`conf`	A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers. CICC Tina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune
2010	—	`conf`	A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. ISSCC Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto
2010	J	`jnl`	Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. IEICE Trans. Electron. Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2009	J	`jnl`	A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. IEEE J. Solid State Circuits Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2009	—	`conf`	A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. ISSCC Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2009	—	`conf`	Split capacitor DAC mismatch calibration in successive approximation ADC. CICC Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2008	J	`jnl`	20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. IEEE J. Solid State Circuits Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
2008	—	`conf`	A dynamic offset control technique for comparator design in scaled CMOS technology. CICC Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
2008	J	`jnl`	Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI. IEEE Trans. Circuits Syst. I Regul. Pap. Marcus van Ierssel, Hisakatsu Yamaguchi, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
2007	J	`jnl`	18-GHz Clock Distribution Using a Coupled VCO Array. IEICE Trans. Electron. Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
2007	J	`jnl`	A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. IEEE J. Solid State Circuits Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
2007	J	`jnl`	A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance. IEEE J. Solid State Circuits Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
2007	J	`jnl`	A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. IEEE J. Solid State Circuits Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2007	—	`conf`	A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. ISSCC Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2006	—	`conf`	A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. ISSCC Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
2006	—	`conf`	A 3.2Gb/s Semi-Blind-Oversampling CDR. ISSCC Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
2006	—	`conf`	A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers. CICC Ricky Yuen, Marcus van Ierssel, Ali Sheikholeslami, William W. Walker, Hirotaka Tamura
2006	J	`jnl`	Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. IEICE Trans. Electron. Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa
2005	—	`conf`	A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process. CICC Yoshiyasu Doi, Syunitirou Masaki, Takaya Chiba, Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura
2005	J	`jnl`	A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. IEEE J. Solid State Circuits Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda
2005	J	`jnl`	A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE J. Solid State Circuits Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda
2005	J	`jnl`	A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization. IEEE J. Solid State Circuits Hirohito Higashi, Syunitirou Masaki, Masaya Kibune, Satoshi Matsubara, Takaya Chiba, Yoshiyasu Doi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Hirotaka Tamura
2003	J	`jnl`	A CMOS multichannel 10-Gb/s transceiver. IEEE J. Solid State Circuits Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura
1998	J	`jnl`	500-Mb/s nonprecharged data bus for high-speed DRAM's. IEEE J. Solid State Circuits Miyoshi Saito, Junji Ogawa, Hirotaka Tamura, Shigetoshi Wakayama, Hisakatsu Araki, Tsz-Shing Cheung, Kohtaroh Gotoh, Tadao Aikawa, Takaaki Suzuki, Masao Taguchi, Takeshi Imamura