Hiroshi Nakamura

199 papers A* 2A 18B 13C 23Misc 4Journal 61Unranked 76

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Dataflow-Oriented Classification and Performance Analysis of GPU-Accelerated Homomorphic Encryption. CoRR Ai Nozaki, Takuya Kojima, Hideki Takase, Hiroshi Nakamura
2026	J	`jnl`	Toward Ultra-High-Speed, Ultra-Low-Power Cryogenic Superconductor Computing. Computer Koji Inoue, Ilkwon Byun, Masamitsu Tanaka, Yosuke Ueno, Naoki Takeuchi, Satoshi Kawakami, Olivia Chen, Dongmoon Min, Teruo Tanimoto, Takatsugu Ono, Hiroshi Nakamura, Jangwoo Kim
2025	—	`conf`	A Decoupled Coarse-Grained Reconfigurable Architecture by Introducing Data Flow Management Unit. IPDPS (Workshops) Hisako Ito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura
2025	J	`jnl`	An Open-Source Framework for Efficient Side-Channel Analysis on Cryptographic Implementations. IACR Cryptol. ePrint Arch. Takuya Kojima, Masaki Morita, Hideki Takase, Hiroshi Nakamura
2025	B	`conf`	Exploring the Possibility of TypiClust for Low-Budget Federated Active Learning. COMPSAC Yuta Ono, Hiroshi Nakamura, Hideki Takase
2025	J	`jnl`	Exploring the Possibility of TypiClust for Low-Budget Federated Active Learning. CoRR Yuta Ono, Hiroshi Nakamura, Hideki Takase
2025	—	`conf`	Hetero-SplitEE: Split Learning of Neural Networks with Early Exits for Heterogeneous IoT Devices. MCSoC Yuki Oda, Yuta Ono, Hiroshi Nakamura, Hideki Takase
2025	J	`jnl`	Hetero-SplitEE: Split Learning of Neural Networks with Early Exits for Heterogeneous IoT Devices. CoRR Yuki Oda, Yuta Ono, Hiroshi Nakamura, Hideki Takase
2025	—	`conf`	Modeling Memory Usage in Training of Reversible Residual Network for Parallel Distributed Processing. HEART Kensuke Setsu, Ryota Miyagi, Hiroshi Nakamura, Hideki Takase
2025	J	`jnl`	Xai-driven black-box adversarial attacks on network intrusion detectors. Int. J. Inf. Sec. Satoshi Okada, Houda Jmila, Kunio Akashi, Takuho Mitsunaga, Yuji Sekiya, Hideki Takase, Gregory Blanc, Hiroshi Nakamura
2024	—	`conf`	A Resource Allocation Method in Multi-access Edge Computing Environment Based on Deep Reinforcement Learning. MCSoC Huilin Li, Hiroshi Nakamura, Hideki Takase
2024	—	`conf`	A Scalable Mapping Method for Elastic CGRAs. IPDPS (Workshops) Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura
2024	—	`conf`	A Study on Number Theoretic Transform Acceleration on AMD AI Engine. MCSoC Ai Nozaki, Takuya Kojima, Hiroshi Nakamura, Hideki Takase
2024	J	`jnl`	C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms. CoRR Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
2024	J	`jnl`	High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture. CoRR Yosuke Ueno, Taku Saito, Teruo Tanimoto, Yasunari Suzuki, Yutaka Tabuchi, Shuhei Tamate, Hiroshi Nakamura
2024	J	`jnl`	Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines. IEEE Comput. Archit. Lett. Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
2024	—	`conf`	MLIR-Based Homomorphic Encryption Compiler for GPU. HEART Ai Nozaki, Takuya Kojima, Hiroshi Nakamura, Hideki Takase
2024	J	`jnl`	SFQ counter-based precomputation for large-scale cryogenic VQE machines. CoRR Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
2024	—	`conf`	XAI-driven Adversarial Attacks on Network Intrusion Detectors. EICC Satoshi Okada, Houda Jmila, Kunio Akashi, Takuho Mitsunaga, Yuji Sekiya, Hideki Takase, Gregory Blanc, Hiroshi Nakamura
2023	J	`jnl`	Adaptive Lossy Data Compression Extended Architecture for Memory Bandwidth Conservation in SpMV. IEICE Trans. Inf. Syst. Siyi Hu, Makiko Ito, Takahide Yoshikawa, Yuan He, Hiroshi Nakamura, Masaaki Kondo
2023	—	`conf`	An Area-Efficient Coarse-Grained Reconfigurable Array Design for Approximate Computing. MCSoC Kaito Kutsuna, Takuya Kojima, Hideki Takase, Hiroshi Nakamura
2023	B	`conf`	An asynchronous federated learning focusing on updated models for decentralized systems with a practical framework. COMPSAC Yusuke Kanamori, Yusuke Yamasaki, Shintaro Hosoai, Hiroshi Nakamura, Hideki Takase
2023	J	`jnl`	An edge re-ordering based acceleration architecture for improving data locality in graph analytics applications. Microprocess. Microsystems Siyi Hu, Masaaki Kondo, Yuan He, Ryuichi Sakamoto, Hao Zhang, Jun Zhou, Hiroshi Nakamura
2023	B	`conf`	ILP Based Mapping for Elastic CGRAs. RTCSA Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura
2023	J	`jnl`	Inter-temperature Bandwidth Reduction in Cryogenic QAOA Machines. CoRR Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
2023	J	`jnl`	Memory-saving LDoS Attacker Detection Algorithms in Zigbee Network. J. Inf. Process. Satoshi Okada, Kunio Akashi, Daisuke Miyamoto, Yuji Sekiya, Hideki Takase, Hiroshi Nakamura
2022	C	`conf`	GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications. PDP Siyi Hu, Masaaki Kondo, Yuan He, Ryuichi Sakamoto, Hao Zhang, Jun Zhou, Hiroshi Nakamura
2022	—	`conf`	Improvement of Signal Power in Intrabody Communication Using an Impedance Adjustment Circuit. GCCE Kiyotaka Hayami, Daichi Kawamoto, Mitsuru Shinagawa, Masayuki Makino, Hiroshi Nakamura, Naoyuki Honma
2022	—	`conf`	mdx: A Cloud Platform for Supporting Data Science and Cross-Disciplinary Research Collaborations. DASC/PiCom/CBDCom/CyberSciTech Toyotaro Suzumura, Akiyoshi Sugiki, Hiroyuki Takizawa, Akira Imakura, Hiroshi Nakamura, Kenjiro Taura, Tomohiro Kudoh, Toshihiro Hanawa, Yuji Sekiya, Hill Hiroki Kobayashi, Yohei Kuga, Ryo Nakamura, Renhe Jiang, Junya Kawase, Masatoshi Hanai, Hiroshi Miyazaki, Tsutomu Ishizaki, Daisuké Shimotoku, Daisuke Miyamoto, Kento Aida, Atsuko Takefusa, Takashi Kurimoto, Koji Sasayama, Naoya Kitagawa, Ikki Fujiwara, Yusuke Tanimura, Takayuki Aoki, Toshio Endo, Satoshi Ohshima, Keiichiro Fukazawa, Susumu Date, Toshihiro Uchibayashi
2022	J	`jnl`	mdx: A Cloud Platform for Supporting Data Science and Cross-Disciplinary Research Collaborations. CoRR Toyotaro Suzumura, Akiyoshi Sugiki, Hiroyuki Takizawa, Akira Imakura, Hiroshi Nakamura, Kenjiro Taura, Tomohiro Kudoh, Toshihiro Hanawa, Yuji Sekiya, Hill Hiroki Kobayashi, Shin Matsushima, Yohei Kuga, Ryo Nakamura, Renhe Jiang, Junya Kawase, Masatoshi Hanai, Hiroshi Miyazaki, Tsutomu Ishizaki, Daisuké Shimotoku, Daisuke Miyamoto, Kento Aida, Atsuko Takefusa, Takashi Kurimoto, Koji Sasayama, Naoya Kitagawa, Ikki Fujiwara, Yusuke Tanimura, Takayuki Aoki, Toshio Endo, Satoshi Ohshima, Keiichiro Fukazawa, Susumu Date, Toshihiro Uchibayashi
2021	Misc	`conf`	Dynamic Power Management for 5G Small Cell Base Station. COMSNETS Yuta Suzuki, Ryuichi Sakamoto, Hiroshi Nakamura
2021	—	`conf`	LDoS Attacker Detection Algorithms in Zigbee Network. iThings/GreenCom/CPSCom/SmartData/Cybermatics Satoshi Okada, Daisuke Miyamoto, Yuji Sekiya, Hideki Takase, Hiroshi Nakamura
2021	—	`conf`	Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes. MCSoC Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura
2021	B	`conf`	New LDoS Attack in Zigbee Network and its Possible Countermeasures. SMARTCOMP Satoshi Okada, Daisuke Miyamoto, Yuji Sekiya, Hiroshi Nakamura
2020	J	`jnl`	A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology. IEEE J. Solid State Circuits Noboru Shibata, Takahisa Kawabe, Taira Shibuya, Mario Sako, Kosuke Yanagidaira, Toshifumi Hashimoto, Hiroki Date, Manabu Sato, Tomoki Nakagawa, Junji Musha, Takatoshi Minamoto, Kazushige Kanda, Mizuki Uda, Dai Nakamura, Katsuaki Sakurai, Takahiro Yamashita, Jieyun Zhou, Ryoichi Tachibana, Teruo Takagiwa, Takahiro Sugimoto, Masatsugu Ogawa, Yusuke Ochi, Takahiro Shimizu, Kazuaki Kawaguchi, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Tadashi Someya, Yasuyuki Kajitani, Yuuki Matsumoto, Jun Nakai, Jumpei Sato, Namasivayam Raghunathan, Yee Lih Koh, Shuo Chen, Juan Lee, Hiroaki Nasu, Hiroshi Sugawara, Koji Hosono, Toshiki Hisada, Hiroshi Nakamura, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Tomoaki Nakano
2020	J	`jnl`	An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. Takashi Nakada, Hiroyuki Yanagihashi, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura
2020	—	`conf`	Electric Field Communication using a Wide Metal Plate as the Transmission Path. GCCE Naoya Takahashi, Yoshiki Matsui, Sotaro Sawa, Daichi Kawamoto, Mitsuru Shinagawa, Kohei Hamamura, Hiroshi Nakamura, Naohiro Shimizu, Masaya Sugino
2020	—	`conf`	Slow Scan Attack Detection Based on Communication Behavior. ICCNS Tomoya Yamashita, Daisuke Miyamoto, Yuji Sekiya, Hiroshi Nakamura
2019	—	`conf`	A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. ISSCC Noboru Shibata, Kazushige Kanda, Takahiro Shimizu, Jun Nakai, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Takeshi Nakano, Takahisa Kawabe, Taira Shibuya, Mario Sako, Kosuke Yanagidaira, Toshifumi Hashimoto, Hiroki Date, Manabu Sato, Tomoki Nakagawa, H. Takamoto, Junji Musha, Takatoshi Minamoto, Mizuki Uda, Dai Nakamura, Katsuaki Sakurai, Takahiro Yamashita, Jieyun Zhou, Ryoichi Tachibana, Teruo Takagiwa, Takahiro Sugimoto, Mikio Ogawa, Yusuke Ochi, Kazuaki Kawaguchi, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Tadashi Someya, Yasuyuki Kajitani, Yuuki Matsumoto, Naohito Morozumi, Jumpei Sato, Namas Raghunathan, Yee Lih Koh, Shuo Chen, Juan Lee, Hiroaki Nasu, Hiroshi Sugawara, Koji Hosono, Toshiki Hisada, T. Kaneko, Hiroshi Nakamura
2019	—	`conf`	A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology. ISSCC Chang Hua Siau, Kwang-Ho Kim, Seungpil Lee, Katsuaki Isobe, Noboru Shibata, Kapil Verma, Takuya Ariki, Jason Li, Jong Yuh, Anirudh Amarnath, Qui Nguyen, Ohwon Kwon, Stanley Jeong, Heguang Li, Hua-Ling Hsu, Taiyuan Tseng, Steve Choi, Siddhesh Darne, Pradeep Anantula, Alex Yap, Hardwell Chibvongodze, Hitoshi Miwa, Minoru Yamashita, Mitsuyuki Watanabe, Koichiro Hayashi, Yosuke Kato, Toru Miwa, Jang Yong Kang, Masatoshi Okumura, Naoki Ookuma, Muralikrishna Balaga, Venky Ramachandra, Aki Matsuda, Swaroop Kulkarni, Raghavendra Rachineni, Pai K. Manjunath, Masahito Takehara, Anil Pai, Srinivas Rajendra, Toshiki Hisada, Ryo Fukuda, Naoya Tokiwa, Kazuaki Kawaguchi, Masashi Yamaoka, Hiromitsu Komai, Takatoshi Minamoto, Masaki Unno, Susumu Ozawa, Hiroshi Nakamura, Tomoo Hishida, Yasuyuki Kajitani, Lei Lin
2019	—	`conf`	Distinction of Heart Sound and Respiratory Sound Using Body Conduction Sound Sensor Based on HPSS. ACIT Kaede Torii, Shota Nakashima, Hiroshi Nakamura, Tetsuo Ooyagi, Kanya Tanaka, Hiroyuki Yagami
2019	A	`conf`	Electric Field Communication using a Car Body as a Transmission Medium. ICST Yoshiki Matsui, Kenta Nezu, Naoya Takahashi, Koki Yoshioka, Mitsuru Shinagawa, Kohei Hamamura, Hiroshi Nakamura, Naohiro Shimizu
2019	C	`conf`	Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement Learning. ICCD Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura
2018	—	`conf`	A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. ISSCC Hiroshi Maejima, Kazushige Kanda, Susumu Fujimura, Teruo Takagiwa, Susumu Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Naohito Morozumi, Ryo Fukuda, Yuui Shimizu, Toshifumi Hashimoto, Xu Li, Yuki Shimizu, Kenichi Abe, Tadashi Yasufuku, Takatoshi Minamoto, Hiroshi Yoshihara, Takahiro Yamashita, Kazuhiko Satou, Takahiro Sugimoto, Fumihiro Kono, Mitsuhiro Abe, Tomoharu Hashiguchi, Masatsugu Kojima, Yasuhiro Suematsu, Takahiro Shimizu, Akihiro Imamoto, Naoki Kobayashi, Makoto Miakashi, Kouichirou Yamaguchi, Sanad Bushnaq, Hicham Haibi, Masatsugu Ogawa, Yusuke Ochi, Kenro Kubota, Taichi Wakui, Dong He, Weihan Wang, Hiroe Minagawa, Tomoko Nishiuchi, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Yee Lih Koh, Feng Lu, Venky Ramachandra, Srinivas Rajendra, Steve Choi, Keyur Payak, Namas Raghunathan, Spiros Georgakis, Hiroshi Sugawara, Seungpil Lee, Takuya Futatsuyama, Koji Hosono, Noboru Shibata, Toshiki Hisada, Tetsuya Kaneko, Hiroshi Nakamura
2017	J	`jnl`	Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning. ACM Trans. Embed. Comput. Syst. Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura
2017	J	`jnl`	An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation. IEICE Trans. Inf. Syst. Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
2017	—	`conf`	Building block multi-chip systems using inductive coupling through chip interface. ISOCC Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki
2017	C	`conf`	Dual notch-type high-order frinction-free force observers for force sensorless fine force control. IECON Toshimasa Miyazaki, Naoki Kamiya, Hiroshi Nakamura, Yuki Yokokura, Kiyoshi Ohishi
2017	C	`conf`	Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors. VLSI-SoC Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Nakamura, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi
2017	—	`conf`	Heart Rate and Heart Rate Variability Measuring System by Using Smartphone. ACIT/CSII/BCD Muhammad Khairul Nizar Bin Khairuddin, Kazuhiro Nakamoto, Hiroshi Nakamura, Kanya Tanaka, Shota Nakashima
2017	—	`conf`	Scalable deep neural network accelerator cores with cubic integration using through chip interface. ISOCC Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano
2017	J	`jnl`	Scenario Analysis for Clean Energy Vehicles in UK Considering Introduction of Renewable Energy Sources. Int. J. Autom. Technol. Hiroshi Nakamura, Masaru Nakano
2017	—	`conf`	The Design and Implementation of Scalable Deep Neural Network Accelerator Cores. MCSoC Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano
2016	—	`conf`	7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
2016	J	`jnl`	A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. IEICE Trans. Inf. Syst. Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
2016	J	`jnl`	An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki
2016	C	`conf`	An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. VLSI-SoC Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
2016	C	`conf`	Fine force control without force sensor based on reaction force estimation system considering static friction and kinetic friction. IECON Hiroshi Nakamura, Kiyoshi Ohishi, Yuki Yokokura, Toshimasa Miyazaki, Akifumi Tsukamoto
2016	—	`conf`	Normally-off power management for sensor nodes of global navigation satellite system. ISOCC Takashi Nakada, Hiroshi Nakamura, Toshifumi Nakamoto, Toru Shimizu
2015	J	`jnl`	A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki
2015	—	`conf`	Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks. DSDIS Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura
2015	C	`conf`	Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. ICCD Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura
2015	C	`conf`	Position sensorless control with accelerometer for linear and curvilinear synchronous motor. IECON Yoshiyasu Takase, Hiroshi Nakamura, Minoru Koga, Toru Shikayama, Akihito Toyota
2015	A	`conf`	Profile-based power shifting in interconnection networks with on/off links. SC Shinobu Miwa, Hiroshi Nakamura
2015	C	`conf`	Runtime multi-optimizations for energy efficient on-chip interconnections1. ICCD Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
2015	B	`conf`	Suggestion-based interactive video digest design by user-system cooperative evolution. CEC Hiroshi Nakamura, Satoshi Ono
2014	J	`jnl`	Area-Efficient Microarchitecture for Reinforcement of Turbo Mode. IEICE Trans. Inf. Syst. Shinobu Miwa, Takara Inoue, Hiroshi Nakamura
2014	—	`conf`	Data-aware power management for periodic real-time systems with non-volatile memory. NVMSA Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
2014	J	`jnl`	Design Aid of Multi-core Embedded Systems with Energy Model. Inf. Media Technol. Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
2014	—	`conf`	Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2014	A	`conf`	Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura
2014	—	`conf`	Normally-off computing project: Challenges and opportunities. ASP-DAC Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa
2014	J	`jnl`	Performance estimation of high performance computing systems with Energy Efficient Ethernet technology. Comput. Sci. Res. Dev. Shinobu Miwa, Sho Aita, Hiroshi Nakamura
2014	C	`conf`	Proposal of position sensorless control and torque ripple compensation based on torque sensor feedback. IECON Yoshiyasu Takase, Hiroshi Nakamura, Takashi Mamba, Fei Zhao
2014	—	`conf`	Step climbing control of wheeled robot based on slip ratio taking account of work load shift by anti-dive force of suspensions and accerelation. AMC Masaki Higashino, Hiroshi Fujimoto, Yoshiyasu Takase, Hiroshi Nakamura
2014	—	`conf`	Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. ISSoC Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2014	—	`conf`	Video summarization support by Interactive Evolutionary Computation. SCIS&ISIS Hiroshi Nakamura, Satoshi Ono
2013	J	`jnl`	A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	A	`conf`	D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
2013	B	`conf`	Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	J	`jnl`	Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki
2013	J	`jnl`	Imbalance of CPU temperatures in a blade system and its impact for power consumption of fans. Clust. Comput. Yuetsu Kodama, Satoshi Itoh, Toshiyuki Shimizu, Satoshi Sekiguchi, Hiroshi Nakamura, Naohiko Mori
2013	B	`conf`	Integrating Multi-GPU Execution in an OpenACC Compiler. ICPP Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Naoya Maruyama
2013	B	`conf`	McRouter: Multicast within a router for high performance network-on-chips. PACT Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
2013	C	`conf`	Performance modeling for designing NoC-based multiprocessors. RSP Takashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura
2013	C	`conf`	Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping. ICCD Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
2013	—	`conf`	Predict-More Router: A Low Latency NoC Router with More Route Predictions. IPDPS Workshops Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
2013	C	`conf`	Proposal of step climbing of wheeled robot using slip ratio control. IECON Masaki Higashino, Hiroshi Fujimoto, Yoshiyasu Takase, Hiroshi Nakamura
2012	—	`conf`	A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2012	—	`conf`	A novel power-gating scheme utilizing data retentiveness on caches. ACM Great Lakes Symposium on VLSI Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
2012	J	`jnl`	Adaptive Data Compression on 3D Network-on-Chips. Inf. Media Technol. Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura
2012	B	`conf`	CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012	—	`conf`	Communication Library to Overlap Computation and Communication for OpenCL Application. IPDPS Workshops Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura
2012	—	`conf`	Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012	—	`conf`	Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. ISQED Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
2012	J	`jnl`	Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
2012	—	`ch.`	Geyser. Handbook of Energy-Aware and Green Computing Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, Hiroshi Nakamura
2012	B	`conf`	Scalability-based manycore partitioning. PACT Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura
2012	—	`conf`	Stepwise sleep depth control for run-time leakage power saving. ACM Great Lakes Symposium on VLSI Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
2011	—	`conf`	Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
2011	J	`jnl`	Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
2011	J	`jnl`	Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. Inf. Media Technol. Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
2011	J	`jnl`	Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ Trans. Syst. LSI Des. Methodol. Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
2011	—	`conf`	Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo
2011	A	`conf`	On-chip detection methodology for break-even time of power gated function units. ISLPED Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura
2011	J	`jnl`	Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2011	A	`ed.`	Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011 ISLPED Naehyuck Chang, Hiroshi Nakamura, Koji Inoue, Kenichi Osada, Massimo Poncino
2011	—	`ch.`	Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. Low Power Networks-on-Chip Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano
2011	—	`conf`	SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. COOL Chips Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo
2011	J	`jnl`	Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami
2010	C	`ed.`	16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010, Tokyo, Japan, December 13-15, 2010 PRDC Yutaka Ishikawa, Dong Tang, Hiroshi Nakamura
2010	—	`conf`	Adaptive power gating for function units in a microprocessor. ISQED Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2010	—	`conf`	Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo
2010	—	`conf`	Power Reduction Scheme of Fans in a Blade System by Considering the Imbalance of CPU Temperatures. GreenCom/CPSCom Yuetsu Kodama, Satoshi Itoh, Toshiyuki Shimizu, Satoshi Sekiguchi, Hiroshi Nakamura, Naohiko Mori
2010	—	`conf`	Power consumption and efficiency of cooling in a Data Center. GRID Satoshi Itoh, Yuetsu Kodama, Hiroshi Shimizu, Satoshi Sekiguchi, Hiroshi Nakamura, Naohiko Mori
2010	—	`conf`	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2009	A	`conf`	Cooperative shared resource access control for low-power chip multiprocessors. ISLPED Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
2009	Misc	`conf`	Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
2009	J	`jnl`	Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping. IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
2009	J	`jnl`	Pangea: An Eager Database Replication Middleware guaranteeing Snapshot Isolation without Modification of Database Servers. Proc. VLDB Endow. Takeshi Mishima, Hiroshi Nakamura
2009	—	`conf`	Power-performance modeling of heterogeneous cluster-based web servers. GRID Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, Hiroshi Nakamura
2008	C	`conf`	A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2008	C	`conf`	Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies. PRDC Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura
2008	—	`conf`	Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values. ICDM Workshops Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura
2007	A	`conf`	A High Performance Cluster System Design by Adaptie Power Control. IPDPS Masaaki Kondo, Yoshimichi Ikeda, Hiroshi Nakamura
2007	C	`conf`	A Proposal of New Dependable Database Middleware with Consistency and Concurrency Control. PRDC Takeshi Mishima, Hiroshi Nakamura
2007	—	`conf`	An intra-task dvfs technique based on statistical analysis of hardware events. Conf. Computing Frontiers Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura
2007	A	`conf`	Fast Abstracts. DSN Hiroshi Nakamura
2007	J	`jnl`	Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. SIGARCH Comput. Archit. News Masaaki Kondo, Hiroshi Sasaki, Hiroshi Nakamura
2007	A	`conf`	Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
2007	C	`conf`	Power reduction of chip multi-processors using shared resource control cooperating with DVFS. ICCD Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
2006	—	`conf`	A System Assisting Acquisition of Japanese Expressions Through Read-Write-Hear-Speaking and Comparing Between Use Cases of Relevant Expressions. KES (2) Kohji Itoh, Hiroshi Nakamura, Shunsuke Unno, Jun'ichi Kakegawa
2006	J	`jnl`	Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
2006	A	`conf`	Energy-efficient dynamic instruction scheduling logic through instruction grouping. ISLPED Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
2006	A	`conf`	MegaProto/E: power-aware high-performance cluster with commodity technology. IPDPS Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, Hiroshi Nakashima, Hiroshi Nakamura, Satoshi Matsuoka, Yoshihiko Hotta
2006	J	`jnl`	Noise Reduction from Genotyping Microarrays Using Probe Level Information. Silico Biol. Daisuke Komura, Kunihiro Nishimura, Shumpei Ishikawa, Binaya Panda, Jing Huang, Hiroshi Nakamura, Sigeo Ihara, Michitaka Hirose, Keith W. Jones, Hiroyuki Aburatani
2005	A*	`conf`	A Small, Fast and Low-Power Register File by Bit-Partitioning. HPCA Masaaki Kondo, Hiroshi Nakamura
2005	—	`conf`	Dynamic Instruction Cascading on GALS Microprocessors. PATMOS Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
2005	—	`conf`	Empirical Study for Optimization of Power-Performance with On-Chip Memory. ISHPC Chikafumi Takahashi, Mitsuhisa Sato, Daisuke Takahashi, Taisuke Boku, Hiroshi Nakamura, Masaaki Kondo, Motonobu Fujita
2005	A	`conf`	MegaProto: 1 TFlops/10kW Rack Is Feasible Even with Only Commodity Technology. SC Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, Yoshihiko Hotta
2005	A	`conf`	MegaProto: A Low-Power and Compact Cluster for High-Performance Computing. IPDPS Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, Yoshihiko Hotta
2005	J	`jnl`	Multidimensional support vector machines for visualization of gene expression data. Bioinform. Daisuke Komura, Hiroshi Nakamura, Shuichi Tsutsumi, Hiroyuki Aburatani, Sigeo Ihara
2005	B	`conf`	Secret sequence comparison on public grid computing resources. CCGRID Ken-ichi Kurata, Hiroshi Nakamura, Vincent Breton
2004	—	`conf`	Data Movement Optimization for Software-Controlled On-Chip Memory. Interaction between Compilers and Computer Architectures Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura
2004	—	`conf`	Dynamic Processor Throttling for Power Efficient Computations. PACS Masaaki Kondo, Hiroshi Nakamura
2004	J	`jnl`	Grid as a bioinformatic tool. Parallel Comput. Nicolas Jacq, Christophe Blanchet, Christophe Combet, Emmanuel Cornillot, Laurent Duret, Ken-ichi Kurata, Hiroshi Nakamura, T. Silvestre, Vincent Breton
2004	Misc	`conf`	Multidimensional support vector machines for visualization of gene expression data. SAC Daisuke Komura, Hiroshi Nakamura, Shuichi Tsutsumi, Hiroyuki Aburatani, Sigeo Ihara
2004	—	`conf`	SCIMA-SMP: on-chip memory processor architecture for SMP. WMPI Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato
2004	C	`conf`	Secret sequence comparison in distributed computing environments by interval sampling. CIBCB Ken-ichi Kurata, Vincent Breton, Hiroshi Nakamura
2004	B	`conf`	Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
2003	B	`conf`	A Method to Find Uniq e Sequences on Distrib ted Genomic Databases. CCGRID Ken-ichi Kurata, Vincent Breton, Hiroshi Nakamura
2003	—	`conf`	A zero-time-overhead asynchronous four-phase controller. ISCAS (5) Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya
2003	—	`conf`	Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
2003	—	`conf`	Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya
2003	A	`conf`	Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. DATE Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya
2003	—	`conf`	Logic optimization for asynchronous speed independent controllers using transduction method. ASP-DAC Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya
2003	—	`conf`	Performance optimization of synchronous control units for datapaths with variable delay arithmetic units. ASP-DAC Euiseok Kim, Dong-Ik Lee, Hiroshi Saito, Hiroshi Nakamura, Jeong-Gun Lee, Takashi Nanya
2003	J	`jnl`	Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nattha Sretasereekul, Hiroshi Saito, Euiseok Kim, Metehan Özcan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
2002	J	`jnl`	A 125-mm IEEE J. Solid State Circuits Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Che
2002	—	`conf`	Cache Line Impact on 3D PDE Solvers. ISHPC Masaaki Kondo, Mitsugu Iwamoto, Hiroshi Nakamura
2002	J	`jnl`	Circuit techniques for a 1.8-V-only NAND flash memory. IEEE J. Solid State Circuits Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura
2002	—	`conf`	Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. APCCAS (1) T. Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura
2002	C	`conf`	Formal Verification of a Pipelined Processor with New Memory. PRDC Hiroshi Nakamura, Takanori Arai, Masahiro Fujita
2002	—	`conf`	Logic Optimization for Asynchronous SI Controllers using Transduction Method. IWLS Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya
2002	Misc	`conf`	Rapid Analysis of Specificity of PCR Product on the Whole Genome. PDPTA Ken-ichi Kurata, Christian Saguez, Gerald Dine, Hiroshi Nakamura
2002	J	`jnl`	Software-controlled on-chip memory for high-performance and low-power computing. SIGARCH Comput. Archit. News Masaaki Kondo, Motonobu Fujita, Hiroshi Nakamura
2001	—	`conf`	Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ASYNC Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno
2001	—	`conf`	The standard SpecC language. ISSS Masahiro Fujita, Hiroshi Nakamura
2000	J	`jnl`	Real-time FEM Control System for Connected Piezoelectric Actuators. J. Robotics Mechatronics Daigoro Isobe, Hiroshi Nakamura, Ryuta Shimizu
2000	C	`conf`	SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. ICCD Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku
2000	—	`conf`	Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. Intelligent Memory Systems Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku
1999	J	`jnl`	A 130-mm/ IEEE J. Solid State Circuits Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui
1999	J	`jnl`	Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. IEEE Trans. Computers Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
1999	J	`jnl`	CP-PACS: A massively parallel processor at the University of Tsukuba. Parallel Comput. Kisaburo Nakazawa, Hiroshi Nakamura, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita
1999	J	`jnl`	Performance of lattice QCD programs on CP-PACS. Parallel Comput. Sinya Aoki, R. Burkhalter, Kazuyuki Kanaya, T. Yoshié, Taisuke Boku, Hiroshi Nakamura, Yoshiyuki Yamashita
1998	J	`jnl`	A GaAs upconverter MMIC with an automatic gain control amplifier for 1.9 GHz PHS. IEEE J. Solid State Circuits Huainan Ma, Sher Jiun Fang, Fujiang Lin, Khen-Sang Tan, Junichi Shibata, Atsushi Tamura, Hiroshi Nakamura
1998	J	`jnl`	Applying ATM to mobile infrastructure networks. IEEE Commun. Mag. Hiroshi Nakamura, Hisakazu Tsuboya, Masatomo Nakano, Akihisa Nakajima
1997	J	`jnl`	A 120-mm IEEE J. Solid State Circuits Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto
1997	C	`conf`	A Data Alignment Technique for Improving Cache Performance. ICCD Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
1997	—	`conf`	Advanced processor design using hardware description language AIDL. ASP-DAC Takayuki Morimoto, Kazushi Saito, Hiroshi Nakamura, Taisuke Boku, Kisaburo Nakazawa
1997	A	`conf`	CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations. International Conference on Supercomputing Taisuke Boku, Ken'ichi Itakura, Hiroshi Nakamura, Kisaburo Nakazawa
1997	—	`conf`	Improving cache Performance Through Tiling and Data Alignment. IRREGULAR Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
1996	J	`jnl`	A double-level-V IEEE J. Solid State Circuits Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura
1996	J	`jnl`	Adaptive routing technique on hypercrossbar network and its evaluation. Syst. Comput. Jpn. Taisuke Boku, Kisaburo Nakazawa, Hiroshi Nakamura, Takeshi Sone, Takeshi Mishima, Ken'ichi Itakura
1995	J	`jnl`	A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM. IEEE J. Solid State Circuits Yoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto
1994	J	`jnl`	A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. IEEE J. Solid State Circuits Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara
1994	—	`conf`	Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers. HICSS (1) Hiroshi Nakamura, Kisaburo Nakazawa, Hang Li, Hiromitsu Imori, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita
1993	A	`conf`	A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. International Conference on Supercomputing Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita
1992	A	`conf`	Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline. SC Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori, Shun Kawabe
1990	A*	`conf`	A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka
1990	—	`conf`	A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV (DIMACS/AMS volume) Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka
1990	C	`conf`	Practical design assistance at register transfer level using a data path verifier. ICCD Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka
1989	—	`conf`	Logic Design Assistence Using Temporal Logic Based Language Tokio. LP Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita, Hidehiko Tanaka
1987	J	`jnl`	Multilevel QAM Modulation Techniques for Digital Microwave Radios. IEEE J. Sel. Areas Commun. Yoshimasa Daido, Sadao Takenaka, Eisuke Fukuda, Toshiaki Sakane, Hiroshi Nakamura
1986	J	`jnl`	Theoretical Evalution of Signatures and CNR Penalties Caused by Modem Impairments in Multilevel QAM Digital Radio Modems. IEEE Trans. Commun. Yoshimasa Daido, Eisuke Fukuda, Yukio Takeda, Hiroshi Nakamura
1985	—	`conf`	Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis. LP Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko Tanaka, Tohru Moto-Oka
1984	—	`conf`	A New 4 GHz 90 Mbps Digital Radio System Using 64-QAM Modulation. ICC (2) Sadao Takenaka, Yukio Takeda, Toshiaki Sakane, Hiroshi Nakamura, N. Toyonaga